| /freebsd-10-stable/contrib/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 95 case X86::ESI: case X86::R15: return 5; in getCompactUnwindRegNum()
578 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
615 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
651 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
687 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
688 return X86::R15; in getX86SubSuperRegister()
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| D | X86CallingConv.td | 151 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
336 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
349 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
592 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
597 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
601 R11, R12, R13, R14, R15, RBP,
606 R13, R14, R15,
610 R12, R13, R14, R15,
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| D | X86RegisterInfo.td | 147 def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>;
308 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
340 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
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| /freebsd-10-stable/contrib/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 19 // i16 are returned in registers R15, R14, R13, R12
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| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 79 def R15 : Ri<15, "r15">, DwarfRegNum<[15]>;
110 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
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| /freebsd-10-stable/contrib/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 185 ENTRY(R15)
203 ENTRY(R15)
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| /freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 142 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
151 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
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| D | PPCFrameLowering.h | 203 {PPC::R15, -68}, in getCalleeSavedSpillSlots()
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| /freebsd-10-stable/sys/amd64/amd64/ |
| D | bpf_jit_machdep.h | 55 #define R15 7 macro
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| /freebsd-10-stable/contrib/llvm/lib/Target/R600/ |
| D | AMDILRegisterInfo.td | 37 def R15 : AMDILReg<15, "r15">, DwarfRegNum<[15]>;
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| /freebsd-10-stable/contrib/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 672 case X86::R12: case X86::R13: case X86::R14: case X86::R15: in isX86_64ExtendedReg()
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| D | X86AsmBackend.cpp | 605 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCompactUnwindRegNum()
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| /freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 86 /// together with R14 and R15 in one prolog instruction.
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| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 235 // or SP (R13 or R15) are used. The ARM ISA refers to these operands
248 // The high registers in thumb mode, R8-R15.
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| /freebsd-10-stable/contrib/subversion/subversion/libsvn_subr/ |
| D | win32_crashrpt.c | 252 context->R12, context->R13, context->R14, context->R15); in write_process_info()
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| /freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 39 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
50 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
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| /freebsd-10-stable/contrib/gdb/gdb/ |
| D | wince.c | 233 context_offset (R15),
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| /freebsd-10-stable/contrib/ncurses/misc/ |
| D | emx.src | 733 # The <kf31>...<kf45> keys are R1-R15. We treat some of these in accordance
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| D | terminfo.src | 4111 # The <kf31>...<kf45> keys are R1-R15. We treat some of these in accordance
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| /freebsd-10-stable/contrib/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 909 case X86::R15: return X86::R15D; in getGR32FromGR64()
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| /freebsd-10-stable/contrib/llvm/include/llvm/Target/ |
| D | Target.td | 226 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
|