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Searched refs:R11 (Results 1 – 25 of 36) sorted by relevance

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/freebsd-10-stable/contrib/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td37 def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
51 R11)>;
57 R11, CP, DP, SP, LR)> {
DXCoreCallingConv.td27 // The 'nest' parameter, if any, is passed in R11.
28 CCIfNest<CCAssignToReg<[R11]>>,
DXCoreInstrInfo.td621 let Uses = [R11], isCall=1 in
635 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
639 let Defs = [R11], isReMaterializable = 1 in
641 [(set R11, (cprelwrapper tglobaladdr:$a))]>;
643 let Defs = [R11] in
668 let Defs = [R11], isReMaterializable = 1 in {
673 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
682 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
686 [(set R11, (pcrelwrapper tblockaddress:$a))]>;
691 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
[all …]
DXCoreFrameLowering.cpp105 loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII); in emitPrologue()
/freebsd-10-stable/contrib/llvm/lib/Transforms/InstCombine/
DInstCombineAndOrXor.cpp596 Value *R11,*R12; in foldLogOpOfMaskedICmpsHelper() local
598 if (decomposeBitTestICmp(RHS, RHSCC, R11, R12, R2)) { in foldLogOpOfMaskedICmpsHelper()
599 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in foldLogOpOfMaskedICmpsHelper()
600 A = R11; D = R12; in foldLogOpOfMaskedICmpsHelper()
602 A = R12; D = R11; in foldLogOpOfMaskedICmpsHelper()
608 if (!match(R1, m_And(m_Value(R11), m_Value(R12)))) { in foldLogOpOfMaskedICmpsHelper()
611 R11 = R1; in foldLogOpOfMaskedICmpsHelper()
615 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in foldLogOpOfMaskedICmpsHelper()
616 A = R11; D = R12; E = R2; ok = true; in foldLogOpOfMaskedICmpsHelper()
618 A = R12; D = R11; E = R2; ok = true; in foldLogOpOfMaskedICmpsHelper()
[all …]
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.h45 case R8: case R9: case R10: case R11: in isARMArea1Register()
56 case R8: case R9: case R10: case R11: in isARMArea2Register()
DARMCallingConv.td99 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
194 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
201 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
225 // FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and
228 def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>;
DThumb1FrameLowering.cpp135 case ARM::R11: in emitPrologue()
DARMRegisterInfo.td73 def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
339 (add R1, R3, R5, R7, R9, R11, SP)]>;
DARMBaseRegisterInfo.cpp48 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), in ARMBaseRegisterInfo()
/freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td75 def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
108 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
149 R10, R11, R29, R30, R31)> {
DHexagonRegisterInfo.h37 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
/freebsd-10-stable/contrib/llvm/lib/Target/X86/
DX86RegisterInfo.cpp570 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: in getX86SubSuperRegister()
607 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: in getX86SubSuperRegister()
643 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: in getX86SubSuperRegister()
679 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: in getX86SubSuperRegister()
680 return X86::R11; in getX86SubSuperRegister()
DX86InstrControl.td259 // __chkstk(MSVC): clobber R10, R11 and EFLAGS.
260 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
261 let Defs = [RAX, R10, R11, RSP, EFLAGS],
DX86RegisterInfo.td143 def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>;
339 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
366 R8, R9, R11, RIP)>;
368 R8, R9, R11)>;
DX86FrameLowering.cpp104 X86::R8, X86::R9, X86::R10, X86::R11, 0 in findDeadCallerSavedReg()
1129 return Primary ? X86::R11 : X86::R12; in GetScratchRegister()
1303 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11) in adjustForSegmentedStacks()
1306 MF.getRegInfo().setPhysRegUsed(X86::R11); in adjustForSegmentedStacks()
DX86CallingConv.td601 R11, R12, R13, R14, R15, RBP,
/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/
DPPCAsmPrinter.cpp938 OutStreamer.EmitInstruction(MCInstBuilder(PPC::MFLR).addReg(PPC::R11)); in EmitFunctionStubs()
942 .addReg(PPC::R11) in EmitFunctionStubs()
943 .addReg(PPC::R11) in EmitFunctionStubs()
954 .addReg(PPC::R11)); in EmitFunctionStubs()
998 .addReg(PPC::R11) in EmitFunctionStubs()
1008 .addReg(PPC::R11)); in EmitFunctionStubs()
/freebsd-10-stable/contrib/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h181 ENTRY(R11) \
199 ENTRY(R11) \
/freebsd-10-stable/sys/amd64/amd64/
Dbpf_jit_machdep.h51 #define R11 3 macro
/freebsd-10-stable/contrib/llvm/lib/Target/R600/
DAMDILRegisterInfo.td33 def R11 : AMDILReg<11, "r11">, DwarfRegNum<[11]>;
/freebsd-10-stable/contrib/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h671 case X86::R8: case X86::R9: case X86::R10: case X86::R11: in isX86_64ExtendedReg()
/freebsd-10-stable/contrib/subversion/subversion/libsvn_subr/
Dwin32_crashrpt.c249 context->R8, context->R9, context->R10, context->R11); in write_process_info()
/freebsd-10-stable/contrib/gdb/gdb/
Dwince.c229 context_offset (R11),
360 context_offset (R11),
/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp38 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
49 PPC::R8, PPC::R9, PPC::R10, PPC::R11,

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