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Searched refs:PPC405 (Results 1 – 6 of 6) sorted by relevance

/freebsd-10-stable/contrib/binutils/opcodes/
Dppc-opc.c1621 #define PPC405 PPC403 macro
1716 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1717 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1718 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1719 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1720 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1721 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1722 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1723 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1724 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
[all …]
/freebsd-10-stable/contrib/gcc/config/rs6000/
D40x.md25 ;; PPC401 / PPC403 / PPC405 32-bit integer only IU BPU
/freebsd-10-stable/crypto/openssl/
DConfigure615 "vxworks-ppc405","ccppc:-g -msoft-float -mlongcall -DCPU=PPC405 -I\$(WIND_BASE)/target/h:::VXWORKS:…
/freebsd-10-stable/contrib/gcc/
DChangeLog-20012323 * rs6000.h (processor_type): Add PPC405.
2324 (RTX_COSTS): Add PPC405. Correct rs64 and ppc630 multiply costs.
2325 * rs6000.md: Add PPC405 information. Utilize imul2 and imul3 for
2327 * rs6000.c (processor_target_table): Add PPC405.
DChangeLog-200511499 for QImode and HImode, and not PPC405.
13963 * config/rs6000/rs6000.c (rs6000_file_start): Note PPC405 erratum
DChangeLog-200210109 * rs6000-c.c (rs6000_cpu_cpp_builtins): Define __PPC405__ if PPC405.