1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/sys/dev/pci/pcireg.h 306520 2016-09-30 18:47:34Z jhb $ 27 * 28 */ 29 30 /* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass 35 * PCIP_xxx: device programming interface 36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37 * PCID_xxx: device ID 38 * PCIY_xxx: capability identification number 39 * PCIZ_xxx: extended capability identification number 40 */ 41 42 /* some PCI bus constants */ 43 #define PCI_DOMAINMAX 65535 /* highest supported domain number */ 44 #define PCI_BUSMAX 255 /* highest supported bus number */ 45 #define PCI_SLOTMAX 31 /* highest supported slot number */ 46 #define PCI_FUNCMAX 7 /* highest supported function number */ 47 #define PCI_REGMAX 255 /* highest supported config register addr. */ 48 #define PCIE_REGMAX 4095 /* highest supported config register addr. */ 49 #define PCI_MAXHDRTYPE 2 50 51 #define PCIE_ARI_SLOTMAX 0 52 #define PCIE_ARI_FUNCMAX 255 53 54 #define PCI_RID_BUS_SHIFT 8 55 #define PCI_RID_SLOT_SHIFT 3 56 #define PCI_RID_FUNC_SHIFT 0 57 58 #define PCI_RID(bus, slot, func) \ 59 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 60 (((slot) & PCI_SLOTMAX) << PCI_RID_SLOT_SHIFT) | \ 61 (((func) & PCI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 62 63 #define PCI_ARI_RID(bus, func) \ 64 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 65 (((func) & PCIE_ARI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 66 67 #define PCI_RID2BUS(rid) (((rid) >> PCI_RID_BUS_SHIFT) & PCI_BUSMAX) 68 #define PCI_RID2SLOT(rid) (((rid) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX) 69 #define PCI_RID2FUNC(rid) (((rid) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX) 70 71 #define PCIE_ARI_SLOT(func) (((func) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX) 72 #define PCIE_ARI_FUNC(func) (((func) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX) 73 74 /* PCI config header registers for all devices */ 75 76 #define PCIR_DEVVENDOR 0x00 77 #define PCIR_VENDOR 0x00 78 #define PCIR_DEVICE 0x02 79 #define PCIR_COMMAND 0x04 80 #define PCIM_CMD_PORTEN 0x0001 81 #define PCIM_CMD_MEMEN 0x0002 82 #define PCIM_CMD_BUSMASTEREN 0x0004 83 #define PCIM_CMD_SPECIALEN 0x0008 84 #define PCIM_CMD_MWRICEN 0x0010 85 #define PCIM_CMD_PERRESPEN 0x0040 86 #define PCIM_CMD_SERRESPEN 0x0100 87 #define PCIM_CMD_BACKTOBACK 0x0200 88 #define PCIM_CMD_INTxDIS 0x0400 89 #define PCIR_STATUS 0x06 90 #define PCIM_STATUS_INTxSTATE 0x0008 91 #define PCIM_STATUS_CAPPRESENT 0x0010 92 #define PCIM_STATUS_66CAPABLE 0x0020 93 #define PCIM_STATUS_BACKTOBACK 0x0080 94 #define PCIM_STATUS_MDPERR 0x0100 95 #define PCIM_STATUS_SEL_FAST 0x0000 96 #define PCIM_STATUS_SEL_MEDIMUM 0x0200 97 #define PCIM_STATUS_SEL_SLOW 0x0400 98 #define PCIM_STATUS_SEL_MASK 0x0600 99 #define PCIM_STATUS_STABORT 0x0800 100 #define PCIM_STATUS_RTABORT 0x1000 101 #define PCIM_STATUS_RMABORT 0x2000 102 #define PCIM_STATUS_SERR 0x4000 103 #define PCIM_STATUS_PERR 0x8000 104 #define PCIR_REVID 0x08 105 #define PCIR_PROGIF 0x09 106 #define PCIR_SUBCLASS 0x0a 107 #define PCIR_CLASS 0x0b 108 #define PCIR_CACHELNSZ 0x0c 109 #define PCIR_LATTIMER 0x0d 110 #define PCIR_HDRTYPE 0x0e 111 #define PCIM_HDRTYPE 0x7f 112 #define PCIM_HDRTYPE_NORMAL 0x00 113 #define PCIM_HDRTYPE_BRIDGE 0x01 114 #define PCIM_HDRTYPE_CARDBUS 0x02 115 #define PCIM_MFDEV 0x80 116 #define PCIR_BIST 0x0f 117 118 /* Capability Register Offsets */ 119 120 #define PCICAP_ID 0x0 121 #define PCICAP_NEXTPTR 0x1 122 123 /* Capability Identification Numbers */ 124 125 #define PCIY_PMG 0x01 /* PCI Power Management */ 126 #define PCIY_AGP 0x02 /* AGP */ 127 #define PCIY_VPD 0x03 /* Vital Product Data */ 128 #define PCIY_SLOTID 0x04 /* Slot Identification */ 129 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 130 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 131 #define PCIY_PCIX 0x07 /* PCI-X */ 132 #define PCIY_HT 0x08 /* HyperTransport */ 133 #define PCIY_VENDOR 0x09 /* Vendor Unique */ 134 #define PCIY_DEBUG 0x0a /* Debug port */ 135 #define PCIY_CRES 0x0b /* CompactPCI central resource control */ 136 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 137 #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 138 #define PCIY_AGP8X 0x0e /* AGP 8x */ 139 #define PCIY_SECDEV 0x0f /* Secure Device */ 140 #define PCIY_EXPRESS 0x10 /* PCI Express */ 141 #define PCIY_MSIX 0x11 /* MSI-X */ 142 #define PCIY_SATA 0x12 /* SATA */ 143 #define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 144 145 /* Extended Capability Register Fields */ 146 147 #define PCIR_EXTCAP 0x100 148 #define PCIM_EXTCAP_ID 0x0000ffff 149 #define PCIM_EXTCAP_VER 0x000f0000 150 #define PCIM_EXTCAP_NEXTPTR 0xfff00000 151 #define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID) 152 #define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16) 153 #define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20) 154 155 /* Extended Capability Identification Numbers */ 156 157 #define PCIZ_AER 0x0001 /* Advanced Error Reporting */ 158 #define PCIZ_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */ 159 #define PCIZ_SERNUM 0x0003 /* Device Serial Number */ 160 #define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ 161 #define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ 162 #define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ 163 #define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ 164 #define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */ 165 #define PCIZ_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */ 166 #define PCIZ_RCRB 0x000a /* RCRB Header */ 167 #define PCIZ_VENDOR 0x000b /* Vendor Unique */ 168 #define PCIZ_CAC 0x000c /* Configuration Access Correction -- obsolete */ 169 #define PCIZ_ACS 0x000d /* Access Control Services */ 170 #define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ 171 #define PCIZ_ATS 0x000f /* Address Translation Services */ 172 #define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ 173 #define PCIZ_MRIOV 0x0011 /* Multiple Root IO Virtualization */ 174 #define PCIZ_MULTICAST 0x0012 /* Multicast */ 175 #define PCIZ_PAGE_REQ 0x0013 /* Page Request */ 176 #define PCIZ_AMD 0x0014 /* Reserved for AMD */ 177 #define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */ 178 #define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */ 179 #define PCIZ_TPH_REQ 0x0017 /* TPH Requester */ 180 #define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */ 181 #define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */ 182 #define PCIZ_PMUX 0x001a /* Protocol Multiplexing */ 183 #define PCIZ_PASID 0x001b /* Process Address Space ID */ 184 #define PCIZ_LN_REQ 0x001c /* LN Requester */ 185 #define PCIZ_DPC 0x001d /* Downstream Porto Containment */ 186 #define PCIZ_L1PM 0x001e /* L1 PM Substates */ 187 188 /* config registers for header type 0 devices */ 189 190 #define PCIR_BARS 0x10 191 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 192 #define PCIR_MAX_BAR_0 5 193 #define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 194 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 195 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 196 #define PCIM_BAR_SPACE 0x00000001 197 #define PCIM_BAR_MEM_SPACE 0 198 #define PCIM_BAR_IO_SPACE 1 199 #define PCIM_BAR_MEM_TYPE 0x00000006 200 #define PCIM_BAR_MEM_32 0 201 #define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 202 #define PCIM_BAR_MEM_64 4 203 #define PCIM_BAR_MEM_PREFETCH 0x00000008 204 #define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL 205 #define PCIM_BAR_IO_RESERVED 0x00000002 206 #define PCIM_BAR_IO_BASE 0xfffffffc 207 #define PCIR_CIS 0x28 208 #define PCIM_CIS_ASI_MASK 0x00000007 209 #define PCIM_CIS_ASI_CONFIG 0 210 #define PCIM_CIS_ASI_BAR0 1 211 #define PCIM_CIS_ASI_BAR1 2 212 #define PCIM_CIS_ASI_BAR2 3 213 #define PCIM_CIS_ASI_BAR3 4 214 #define PCIM_CIS_ASI_BAR4 5 215 #define PCIM_CIS_ASI_BAR5 6 216 #define PCIM_CIS_ASI_ROM 7 217 #define PCIM_CIS_ADDR_MASK 0x0ffffff8 218 #define PCIM_CIS_ROM_MASK 0xf0000000 219 #define PCIM_CIS_CONFIG_MASK 0xff 220 #define PCIR_SUBVEND_0 0x2c 221 #define PCIR_SUBDEV_0 0x2e 222 #define PCIR_BIOS 0x30 223 #define PCIM_BIOS_ENABLE 0x01 224 #define PCIM_BIOS_ADDR_MASK 0xfffff800 225 #define PCIR_CAP_PTR 0x34 226 #define PCIR_INTLINE 0x3c 227 #define PCIR_INTPIN 0x3d 228 #define PCIR_MINGNT 0x3e 229 #define PCIR_MAXLAT 0x3f 230 231 /* config registers for header type 1 (PCI-to-PCI bridge) devices */ 232 233 #define PCIR_MAX_BAR_1 1 234 #define PCIR_SECSTAT_1 0x1e 235 236 #define PCIR_PRIBUS_1 0x18 237 #define PCIR_SECBUS_1 0x19 238 #define PCIR_SUBBUS_1 0x1a 239 #define PCIR_SECLAT_1 0x1b 240 241 #define PCIR_IOBASEL_1 0x1c 242 #define PCIR_IOLIMITL_1 0x1d 243 #define PCIR_IOBASEH_1 0x30 244 #define PCIR_IOLIMITH_1 0x32 245 #define PCIM_BRIO_16 0x0 246 #define PCIM_BRIO_32 0x1 247 #define PCIM_BRIO_MASK 0xf 248 249 #define PCIR_MEMBASE_1 0x20 250 #define PCIR_MEMLIMIT_1 0x22 251 252 #define PCIR_PMBASEL_1 0x24 253 #define PCIR_PMLIMITL_1 0x26 254 #define PCIR_PMBASEH_1 0x28 255 #define PCIR_PMLIMITH_1 0x2c 256 #define PCIM_BRPM_32 0x0 257 #define PCIM_BRPM_64 0x1 258 #define PCIM_BRPM_MASK 0xf 259 260 #define PCIR_BIOS_1 0x38 261 #define PCIR_BRIDGECTL_1 0x3e 262 263 #define PCI_PPBMEMBASE(h,l) ((((uint64_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 264 #define PCI_PPBMEMLIMIT(h,l) ((((uint64_t)(h) << 32) + ((l)<<16)) | 0xfffff) 265 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 266 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 267 268 /* config registers for header type 2 (CardBus) devices */ 269 270 #define PCIR_MAX_BAR_2 0 271 #define PCIR_CAP_PTR_2 0x14 272 #define PCIR_SECSTAT_2 0x16 273 274 #define PCIR_PRIBUS_2 0x18 275 #define PCIR_SECBUS_2 0x19 276 #define PCIR_SUBBUS_2 0x1a 277 #define PCIR_SECLAT_2 0x1b 278 279 #define PCIR_MEMBASE0_2 0x1c 280 #define PCIR_MEMLIMIT0_2 0x20 281 #define PCIR_MEMBASE1_2 0x24 282 #define PCIR_MEMLIMIT1_2 0x28 283 #define PCIR_IOBASE0_2 0x2c 284 #define PCIR_IOLIMIT0_2 0x30 285 #define PCIR_IOBASE1_2 0x34 286 #define PCIR_IOLIMIT1_2 0x38 287 #define PCIM_CBBIO_16 0x0 288 #define PCIM_CBBIO_32 0x1 289 #define PCIM_CBBIO_MASK 0x3 290 291 #define PCIR_BRIDGECTL_2 0x3e 292 293 #define PCIR_SUBVEND_2 0x40 294 #define PCIR_SUBDEV_2 0x42 295 296 #define PCIR_PCCARDIF_2 0x44 297 298 #define PCI_CBBMEMBASE(l) ((l) & ~0xfffff) 299 #define PCI_CBBMEMLIMIT(l) ((l) | 0xfffff) 300 #define PCI_CBBIOBASE(l) ((l) & ~0x3) 301 #define PCI_CBBIOLIMIT(l) ((l) | 0x3) 302 303 /* PCI device class, subclass and programming interface definitions */ 304 305 #define PCIC_OLD 0x00 306 #define PCIS_OLD_NONVGA 0x00 307 #define PCIS_OLD_VGA 0x01 308 309 #define PCIC_STORAGE 0x01 310 #define PCIS_STORAGE_SCSI 0x00 311 #define PCIS_STORAGE_IDE 0x01 312 #define PCIP_STORAGE_IDE_MODEPRIM 0x01 313 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 314 #define PCIP_STORAGE_IDE_MODESEC 0x04 315 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08 316 #define PCIP_STORAGE_IDE_MASTERDEV 0x80 317 #define PCIS_STORAGE_FLOPPY 0x02 318 #define PCIS_STORAGE_IPI 0x03 319 #define PCIS_STORAGE_RAID 0x04 320 #define PCIS_STORAGE_ATA_ADMA 0x05 321 #define PCIS_STORAGE_SATA 0x06 322 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01 323 #define PCIS_STORAGE_SAS 0x07 324 #define PCIS_STORAGE_NVM 0x08 325 #define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01 326 #define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02 327 #define PCIS_STORAGE_OTHER 0x80 328 329 #define PCIC_NETWORK 0x02 330 #define PCIS_NETWORK_ETHERNET 0x00 331 #define PCIS_NETWORK_TOKENRING 0x01 332 #define PCIS_NETWORK_FDDI 0x02 333 #define PCIS_NETWORK_ATM 0x03 334 #define PCIS_NETWORK_ISDN 0x04 335 #define PCIS_NETWORK_WORLDFIP 0x05 336 #define PCIS_NETWORK_PICMG 0x06 337 #define PCIS_NETWORK_OTHER 0x80 338 339 #define PCIC_DISPLAY 0x03 340 #define PCIS_DISPLAY_VGA 0x00 341 #define PCIS_DISPLAY_XGA 0x01 342 #define PCIS_DISPLAY_3D 0x02 343 #define PCIS_DISPLAY_OTHER 0x80 344 345 #define PCIC_MULTIMEDIA 0x04 346 #define PCIS_MULTIMEDIA_VIDEO 0x00 347 #define PCIS_MULTIMEDIA_AUDIO 0x01 348 #define PCIS_MULTIMEDIA_TELE 0x02 349 #define PCIS_MULTIMEDIA_HDA 0x03 350 #define PCIS_MULTIMEDIA_OTHER 0x80 351 352 #define PCIC_MEMORY 0x05 353 #define PCIS_MEMORY_RAM 0x00 354 #define PCIS_MEMORY_FLASH 0x01 355 #define PCIS_MEMORY_OTHER 0x80 356 357 #define PCIC_BRIDGE 0x06 358 #define PCIS_BRIDGE_HOST 0x00 359 #define PCIS_BRIDGE_ISA 0x01 360 #define PCIS_BRIDGE_EISA 0x02 361 #define PCIS_BRIDGE_MCA 0x03 362 #define PCIS_BRIDGE_PCI 0x04 363 #define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 364 #define PCIS_BRIDGE_PCMCIA 0x05 365 #define PCIS_BRIDGE_NUBUS 0x06 366 #define PCIS_BRIDGE_CARDBUS 0x07 367 #define PCIS_BRIDGE_RACEWAY 0x08 368 #define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 369 #define PCIS_BRIDGE_INFINIBAND 0x0a 370 #define PCIS_BRIDGE_OTHER 0x80 371 372 #define PCIC_SIMPLECOMM 0x07 373 #define PCIS_SIMPLECOMM_UART 0x00 374 #define PCIP_SIMPLECOMM_UART_8250 0x00 375 #define PCIP_SIMPLECOMM_UART_16450A 0x01 376 #define PCIP_SIMPLECOMM_UART_16550A 0x02 377 #define PCIP_SIMPLECOMM_UART_16650A 0x03 378 #define PCIP_SIMPLECOMM_UART_16750A 0x04 379 #define PCIP_SIMPLECOMM_UART_16850A 0x05 380 #define PCIP_SIMPLECOMM_UART_16950A 0x06 381 #define PCIS_SIMPLECOMM_PAR 0x01 382 #define PCIS_SIMPLECOMM_MULSER 0x02 383 #define PCIS_SIMPLECOMM_MODEM 0x03 384 #define PCIS_SIMPLECOMM_GPIB 0x04 385 #define PCIS_SIMPLECOMM_SMART_CARD 0x05 386 #define PCIS_SIMPLECOMM_OTHER 0x80 387 388 #define PCIC_BASEPERIPH 0x08 389 #define PCIS_BASEPERIPH_PIC 0x00 390 #define PCIP_BASEPERIPH_PIC_8259A 0x00 391 #define PCIP_BASEPERIPH_PIC_ISA 0x01 392 #define PCIP_BASEPERIPH_PIC_EISA 0x02 393 #define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 394 #define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 395 #define PCIS_BASEPERIPH_DMA 0x01 396 #define PCIS_BASEPERIPH_TIMER 0x02 397 #define PCIS_BASEPERIPH_RTC 0x03 398 #define PCIS_BASEPERIPH_PCIHOT 0x04 399 #define PCIS_BASEPERIPH_SDHC 0x05 400 #define PCIS_BASEPERIPH_IOMMU 0x06 401 #define PCIS_BASEPERIPH_OTHER 0x80 402 403 #define PCIC_INPUTDEV 0x09 404 #define PCIS_INPUTDEV_KEYBOARD 0x00 405 #define PCIS_INPUTDEV_DIGITIZER 0x01 406 #define PCIS_INPUTDEV_MOUSE 0x02 407 #define PCIS_INPUTDEV_SCANNER 0x03 408 #define PCIS_INPUTDEV_GAMEPORT 0x04 409 #define PCIS_INPUTDEV_OTHER 0x80 410 411 #define PCIC_DOCKING 0x0a 412 #define PCIS_DOCKING_GENERIC 0x00 413 #define PCIS_DOCKING_OTHER 0x80 414 415 #define PCIC_PROCESSOR 0x0b 416 #define PCIS_PROCESSOR_386 0x00 417 #define PCIS_PROCESSOR_486 0x01 418 #define PCIS_PROCESSOR_PENTIUM 0x02 419 #define PCIS_PROCESSOR_ALPHA 0x10 420 #define PCIS_PROCESSOR_POWERPC 0x20 421 #define PCIS_PROCESSOR_MIPS 0x30 422 #define PCIS_PROCESSOR_COPROC 0x40 423 424 #define PCIC_SERIALBUS 0x0c 425 #define PCIS_SERIALBUS_FW 0x00 426 #define PCIS_SERIALBUS_ACCESS 0x01 427 #define PCIS_SERIALBUS_SSA 0x02 428 #define PCIS_SERIALBUS_USB 0x03 429 #define PCIP_SERIALBUS_USB_UHCI 0x00 430 #define PCIP_SERIALBUS_USB_OHCI 0x10 431 #define PCIP_SERIALBUS_USB_EHCI 0x20 432 #define PCIP_SERIALBUS_USB_XHCI 0x30 433 #define PCIP_SERIALBUS_USB_DEVICE 0xfe 434 #define PCIS_SERIALBUS_FC 0x04 435 #define PCIS_SERIALBUS_SMBUS 0x05 436 #define PCIS_SERIALBUS_INFINIBAND 0x06 437 #define PCIS_SERIALBUS_IPMI 0x07 438 #define PCIP_SERIALBUS_IPMI_SMIC 0x00 439 #define PCIP_SERIALBUS_IPMI_KCS 0x01 440 #define PCIP_SERIALBUS_IPMI_BT 0x02 441 #define PCIS_SERIALBUS_SERCOS 0x08 442 #define PCIS_SERIALBUS_CANBUS 0x09 443 444 #define PCIC_WIRELESS 0x0d 445 #define PCIS_WIRELESS_IRDA 0x00 446 #define PCIS_WIRELESS_IR 0x01 447 #define PCIS_WIRELESS_RF 0x10 448 #define PCIS_WIRELESS_BLUETOOTH 0x11 449 #define PCIS_WIRELESS_BROADBAND 0x12 450 #define PCIS_WIRELESS_80211A 0x20 451 #define PCIS_WIRELESS_80211B 0x21 452 #define PCIS_WIRELESS_OTHER 0x80 453 454 #define PCIC_INTELLIIO 0x0e 455 #define PCIS_INTELLIIO_I2O 0x00 456 457 #define PCIC_SATCOM 0x0f 458 #define PCIS_SATCOM_TV 0x01 459 #define PCIS_SATCOM_AUDIO 0x02 460 #define PCIS_SATCOM_VOICE 0x03 461 #define PCIS_SATCOM_DATA 0x04 462 463 #define PCIC_CRYPTO 0x10 464 #define PCIS_CRYPTO_NETCOMP 0x00 465 #define PCIS_CRYPTO_ENTERTAIN 0x10 466 #define PCIS_CRYPTO_OTHER 0x80 467 468 #define PCIC_DASP 0x11 469 #define PCIS_DASP_DPIO 0x00 470 #define PCIS_DASP_PERFCNTRS 0x01 471 #define PCIS_DASP_COMM_SYNC 0x10 472 #define PCIS_DASP_MGMT_CARD 0x20 473 #define PCIS_DASP_OTHER 0x80 474 475 #define PCIC_OTHER 0xff 476 477 /* Bridge Control Values. */ 478 #define PCIB_BCR_PERR_ENABLE 0x0001 479 #define PCIB_BCR_SERR_ENABLE 0x0002 480 #define PCIB_BCR_ISA_ENABLE 0x0004 481 #define PCIB_BCR_VGA_ENABLE 0x0008 482 #define PCIB_BCR_MASTER_ABORT_MODE 0x0020 483 #define PCIB_BCR_SECBUS_RESET 0x0040 484 #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 485 #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 486 #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 487 #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 488 #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 489 490 #define CBB_BCR_PERR_ENABLE 0x0001 491 #define CBB_BCR_SERR_ENABLE 0x0002 492 #define CBB_BCR_ISA_ENABLE 0x0004 493 #define CBB_BCR_VGA_ENABLE 0x0008 494 #define CBB_BCR_MASTER_ABORT_MODE 0x0020 495 #define CBB_BCR_CARDBUS_RESET 0x0040 496 #define CBB_BCR_IREQ_INT_ENABLE 0x0080 497 #define CBB_BCR_PREFETCH_0_ENABLE 0x0100 498 #define CBB_BCR_PREFETCH_1_ENABLE 0x0200 499 #define CBB_BCR_WRITE_POSTING_ENABLE 0x0400 500 501 /* PCI power manangement */ 502 #define PCIR_POWER_CAP 0x2 503 #define PCIM_PCAP_SPEC 0x0007 504 #define PCIM_PCAP_PMEREQCLK 0x0008 505 #define PCIM_PCAP_DEVSPECINIT 0x0020 506 #define PCIM_PCAP_AUXPWR_0 0x0000 507 #define PCIM_PCAP_AUXPWR_55 0x0040 508 #define PCIM_PCAP_AUXPWR_100 0x0080 509 #define PCIM_PCAP_AUXPWR_160 0x00c0 510 #define PCIM_PCAP_AUXPWR_220 0x0100 511 #define PCIM_PCAP_AUXPWR_270 0x0140 512 #define PCIM_PCAP_AUXPWR_320 0x0180 513 #define PCIM_PCAP_AUXPWR_375 0x01c0 514 #define PCIM_PCAP_AUXPWRMASK 0x01c0 515 #define PCIM_PCAP_D1SUPP 0x0200 516 #define PCIM_PCAP_D2SUPP 0x0400 517 #define PCIM_PCAP_D0PME 0x0800 518 #define PCIM_PCAP_D1PME 0x1000 519 #define PCIM_PCAP_D2PME 0x2000 520 #define PCIM_PCAP_D3PME_HOT 0x4000 521 #define PCIM_PCAP_D3PME_COLD 0x8000 522 523 #define PCIR_POWER_STATUS 0x4 524 #define PCIM_PSTAT_D0 0x0000 525 #define PCIM_PSTAT_D1 0x0001 526 #define PCIM_PSTAT_D2 0x0002 527 #define PCIM_PSTAT_D3 0x0003 528 #define PCIM_PSTAT_DMASK 0x0003 529 #define PCIM_PSTAT_NOSOFTRESET 0x0008 530 #define PCIM_PSTAT_PMEENABLE 0x0100 531 #define PCIM_PSTAT_D0POWER 0x0000 532 #define PCIM_PSTAT_D1POWER 0x0200 533 #define PCIM_PSTAT_D2POWER 0x0400 534 #define PCIM_PSTAT_D3POWER 0x0600 535 #define PCIM_PSTAT_D0HEAT 0x0800 536 #define PCIM_PSTAT_D1HEAT 0x0a00 537 #define PCIM_PSTAT_D2HEAT 0x0c00 538 #define PCIM_PSTAT_D3HEAT 0x0e00 539 #define PCIM_PSTAT_DATASELMASK 0x1e00 540 #define PCIM_PSTAT_DATAUNKN 0x0000 541 #define PCIM_PSTAT_DATADIV10 0x2000 542 #define PCIM_PSTAT_DATADIV100 0x4000 543 #define PCIM_PSTAT_DATADIV1000 0x6000 544 #define PCIM_PSTAT_DATADIVMASK 0x6000 545 #define PCIM_PSTAT_PME 0x8000 546 547 #define PCIR_POWER_BSE 0x6 548 #define PCIM_PMCSR_BSE_D3B3 0x00 549 #define PCIM_PMCSR_BSE_D3B2 0x40 550 #define PCIM_PMCSR_BSE_BPCCE 0x80 551 552 #define PCIR_POWER_DATA 0x7 553 554 /* VPD capability registers */ 555 #define PCIR_VPD_ADDR 0x2 556 #define PCIR_VPD_DATA 0x4 557 558 /* PCI Message Signalled Interrupts (MSI) */ 559 #define PCIR_MSI_CTRL 0x2 560 #define PCIM_MSICTRL_VECTOR 0x0100 561 #define PCIM_MSICTRL_64BIT 0x0080 562 #define PCIM_MSICTRL_MME_MASK 0x0070 563 #define PCIM_MSICTRL_MME_1 0x0000 564 #define PCIM_MSICTRL_MME_2 0x0010 565 #define PCIM_MSICTRL_MME_4 0x0020 566 #define PCIM_MSICTRL_MME_8 0x0030 567 #define PCIM_MSICTRL_MME_16 0x0040 568 #define PCIM_MSICTRL_MME_32 0x0050 569 #define PCIM_MSICTRL_MMC_MASK 0x000E 570 #define PCIM_MSICTRL_MMC_1 0x0000 571 #define PCIM_MSICTRL_MMC_2 0x0002 572 #define PCIM_MSICTRL_MMC_4 0x0004 573 #define PCIM_MSICTRL_MMC_8 0x0006 574 #define PCIM_MSICTRL_MMC_16 0x0008 575 #define PCIM_MSICTRL_MMC_32 0x000A 576 #define PCIM_MSICTRL_MSI_ENABLE 0x0001 577 #define PCIR_MSI_ADDR 0x4 578 #define PCIR_MSI_ADDR_HIGH 0x8 579 #define PCIR_MSI_DATA 0x8 580 #define PCIR_MSI_DATA_64BIT 0xc 581 #define PCIR_MSI_MASK 0x10 582 #define PCIR_MSI_PENDING 0x14 583 584 /* PCI-X definitions */ 585 586 /* For header type 0 devices */ 587 #define PCIXR_COMMAND 0x2 588 #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 589 #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 590 #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 591 #define PCIXM_COMMAND_MAX_READ_512 0x0000 592 #define PCIXM_COMMAND_MAX_READ_1024 0x0004 593 #define PCIXM_COMMAND_MAX_READ_2048 0x0008 594 #define PCIXM_COMMAND_MAX_READ_4096 0x000c 595 #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 596 #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 597 #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 598 #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 599 #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 600 #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 601 #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 602 #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 603 #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 604 #define PCIXM_COMMAND_VERSION 0x3000 605 #define PCIXR_STATUS 0x4 606 #define PCIXM_STATUS_DEVFN 0x000000FF 607 #define PCIXM_STATUS_BUS 0x0000FF00 608 #define PCIXM_STATUS_64BIT 0x00010000 609 #define PCIXM_STATUS_133CAP 0x00020000 610 #define PCIXM_STATUS_SC_DISCARDED 0x00040000 611 #define PCIXM_STATUS_UNEXP_SC 0x00080000 612 #define PCIXM_STATUS_COMPLEX_DEV 0x00100000 613 #define PCIXM_STATUS_MAX_READ 0x00600000 614 #define PCIXM_STATUS_MAX_READ_512 0x00000000 615 #define PCIXM_STATUS_MAX_READ_1024 0x00200000 616 #define PCIXM_STATUS_MAX_READ_2048 0x00400000 617 #define PCIXM_STATUS_MAX_READ_4096 0x00600000 618 #define PCIXM_STATUS_MAX_SPLITS 0x03800000 619 #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 620 #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 621 #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 622 #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 623 #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 624 #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 625 #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 626 #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 627 #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 628 #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 629 #define PCIXM_STATUS_266CAP 0x40000000 630 #define PCIXM_STATUS_533CAP 0x80000000 631 632 /* For header type 1 devices (PCI-X bridges) */ 633 #define PCIXR_SEC_STATUS 0x2 634 #define PCIXM_SEC_STATUS_64BIT 0x0001 635 #define PCIXM_SEC_STATUS_133CAP 0x0002 636 #define PCIXM_SEC_STATUS_SC_DISC 0x0004 637 #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 638 #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 639 #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 640 #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 641 #define PCIXM_SEC_STATUS_VERSION 0x3000 642 #define PCIXM_SEC_STATUS_266CAP 0x4000 643 #define PCIXM_SEC_STATUS_533CAP 0x8000 644 #define PCIXR_BRIDGE_STATUS 0x4 645 #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 646 #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 647 #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 648 #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 649 #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 650 #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 651 #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 652 #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 653 #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 654 #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 655 #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 656 657 /* HT (HyperTransport) Capability definitions */ 658 #define PCIR_HT_COMMAND 0x2 659 #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 660 #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 661 #define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 662 #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 663 #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 664 #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 665 #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 666 #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 667 #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 668 #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 669 #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 670 #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 671 #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 672 #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 673 #define PCIM_HTCAP_GEN3 0xd000 /* 11010 */ 674 #define PCIM_HTCAP_FLE 0xd800 /* 11011 */ 675 #define PCIM_HTCAP_PM 0xe000 /* 11100 */ 676 #define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */ 677 678 /* HT MSI Mapping Capability definitions. */ 679 #define PCIM_HTCMD_MSI_ENABLE 0x0001 680 #define PCIM_HTCMD_MSI_FIXED 0x0002 681 #define PCIR_HTMSI_ADDRESS_LO 0x4 682 #define PCIR_HTMSI_ADDRESS_HI 0x8 683 684 /* PCI Vendor capability definitions */ 685 #define PCIR_VENDOR_LENGTH 0x2 686 #define PCIR_VENDOR_DATA 0x3 687 688 /* PCI EHCI Debug Port definitions */ 689 #define PCIR_DEBUG_PORT 0x2 690 #define PCIM_DEBUG_PORT_OFFSET 0x1FFF 691 #define PCIM_DEBUG_PORT_BAR 0xe000 692 693 /* PCI-PCI Bridge Subvendor definitions */ 694 #define PCIR_SUBVENDCAP_ID 0x4 695 696 /* PCI Express definitions */ 697 #define PCIER_FLAGS 0x2 698 #define PCIEM_FLAGS_VERSION 0x000F 699 #define PCIEM_FLAGS_TYPE 0x00F0 700 #define PCIEM_TYPE_ENDPOINT 0x0000 701 #define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 702 #define PCIEM_TYPE_ROOT_PORT 0x0040 703 #define PCIEM_TYPE_UPSTREAM_PORT 0x0050 704 #define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 705 #define PCIEM_TYPE_PCI_BRIDGE 0x0070 706 #define PCIEM_TYPE_PCIE_BRIDGE 0x0080 707 #define PCIEM_TYPE_ROOT_INT_EP 0x0090 708 #define PCIEM_TYPE_ROOT_EC 0x00a0 709 #define PCIEM_FLAGS_SLOT 0x0100 710 #define PCIEM_FLAGS_IRQ 0x3e00 711 #define PCIER_DEVICE_CAP 0x4 712 #define PCIEM_CAP_MAX_PAYLOAD 0x00000007 713 #define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 714 #define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 715 #define PCIEM_CAP_L0S_LATENCY 0x000001c0 716 #define PCIEM_CAP_L1_LATENCY 0x00000e00 717 #define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 718 #define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 719 #define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 720 #define PCIEM_CAP_FLR 0x10000000 721 #define PCIER_DEVICE_CTL 0x8 722 #define PCIEM_CTL_COR_ENABLE 0x0001 723 #define PCIEM_CTL_NFER_ENABLE 0x0002 724 #define PCIEM_CTL_FER_ENABLE 0x0004 725 #define PCIEM_CTL_URR_ENABLE 0x0008 726 #define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 727 #define PCIEM_CTL_MAX_PAYLOAD 0x00e0 728 #define PCIEM_CTL_EXT_TAG_FIELD 0x0100 729 #define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 730 #define PCIEM_CTL_AUX_POWER_PM 0x0400 731 #define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 732 #define PCIEM_CTL_MAX_READ_REQUEST 0x7000 733 #define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ 734 #define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ 735 #define PCIER_DEVICE_STA 0xa 736 #define PCIEM_STA_CORRECTABLE_ERROR 0x0001 737 #define PCIEM_STA_NON_FATAL_ERROR 0x0002 738 #define PCIEM_STA_FATAL_ERROR 0x0004 739 #define PCIEM_STA_UNSUPPORTED_REQ 0x0008 740 #define PCIEM_STA_AUX_POWER 0x0010 741 #define PCIEM_STA_TRANSACTION_PND 0x0020 742 #define PCIER_LINK_CAP 0xc 743 #define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f 744 #define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 745 #define PCIEM_LINK_CAP_ASPM 0x00000c00 746 #define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 747 #define PCIEM_LINK_CAP_L1_EXIT 0x00038000 748 #define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 749 #define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 750 #define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 751 #define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 752 #define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 753 #define PCIEM_LINK_CAP_PORT 0xff000000 754 #define PCIER_LINK_CTL 0x10 755 #define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 756 #define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 757 #define PCIEM_LINK_CTL_ASPMC_L1 0x0002 758 #define PCIEM_LINK_CTL_ASPMC 0x0003 759 #define PCIEM_LINK_CTL_RCB 0x0008 760 #define PCIEM_LINK_CTL_LINK_DIS 0x0010 761 #define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 762 #define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 763 #define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 764 #define PCIEM_LINK_CTL_ECPM 0x0100 765 #define PCIEM_LINK_CTL_HAWD 0x0200 766 #define PCIEM_LINK_CTL_LBMIE 0x0400 767 #define PCIEM_LINK_CTL_LABIE 0x0800 768 #define PCIER_LINK_STA 0x12 769 #define PCIEM_LINK_STA_SPEED 0x000f 770 #define PCIEM_LINK_STA_WIDTH 0x03f0 771 #define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 772 #define PCIEM_LINK_STA_TRAINING 0x0800 773 #define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 774 #define PCIEM_LINK_STA_DL_ACTIVE 0x2000 775 #define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 776 #define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 777 #define PCIER_SLOT_CAP 0x14 778 #define PCIEM_SLOT_CAP_APB 0x00000001 779 #define PCIEM_SLOT_CAP_PCP 0x00000002 780 #define PCIEM_SLOT_CAP_MRLSP 0x00000004 781 #define PCIEM_SLOT_CAP_AIP 0x00000008 782 #define PCIEM_SLOT_CAP_PIP 0x00000010 783 #define PCIEM_SLOT_CAP_HPS 0x00000020 784 #define PCIEM_SLOT_CAP_HPC 0x00000040 785 #define PCIEM_SLOT_CAP_SPLV 0x00007f80 786 #define PCIEM_SLOT_CAP_SPLS 0x00018000 787 #define PCIEM_SLOT_CAP_EIP 0x00020000 788 #define PCIEM_SLOT_CAP_NCCS 0x00040000 789 #define PCIEM_SLOT_CAP_PSN 0xfff80000 790 #define PCIER_SLOT_CTL 0x18 791 #define PCIEM_SLOT_CTL_ABPE 0x0001 792 #define PCIEM_SLOT_CTL_PFDE 0x0002 793 #define PCIEM_SLOT_CTL_MRLSCE 0x0004 794 #define PCIEM_SLOT_CTL_PDCE 0x0008 795 #define PCIEM_SLOT_CTL_CCIE 0x0010 796 #define PCIEM_SLOT_CTL_HPIE 0x0020 797 #define PCIEM_SLOT_CTL_AIC 0x00c0 798 #define PCIEM_SLOT_CTL_PIC 0x0300 799 #define PCIEM_SLOT_CTL_PCC 0x0400 800 #define PCIEM_SLOT_CTL_EIC 0x0800 801 #define PCIEM_SLOT_CTL_DLLSCE 0x1000 802 #define PCIER_SLOT_STA 0x1a 803 #define PCIEM_SLOT_STA_ABP 0x0001 804 #define PCIEM_SLOT_STA_PFD 0x0002 805 #define PCIEM_SLOT_STA_MRLSC 0x0004 806 #define PCIEM_SLOT_STA_PDC 0x0008 807 #define PCIEM_SLOT_STA_CC 0x0010 808 #define PCIEM_SLOT_STA_MRLSS 0x0020 809 #define PCIEM_SLOT_STA_PDS 0x0040 810 #define PCIEM_SLOT_STA_EIS 0x0080 811 #define PCIEM_SLOT_STA_DLLSC 0x0100 812 #define PCIER_ROOT_CTL 0x1c 813 #define PCIEM_ROOT_CTL_SERR_CORR 0x0001 814 #define PCIEM_ROOT_CTL_SERR_NONFATAL 0x0002 815 #define PCIEM_ROOT_CTL_SERR_FATAL 0x0004 816 #define PCIEM_ROOT_CTL_PME 0x0008 817 #define PCIEM_ROOT_CTL_CRS_VIS 0x0010 818 #define PCIER_ROOT_CAP 0x1e 819 #define PCIEM_ROOT_CAP_CRS_VIS 0x0001 820 #define PCIER_ROOT_STA 0x20 821 #define PCIEM_ROOT_STA_PME_REQID_MASK 0x0000ffff 822 #define PCIEM_ROOT_STA_PME_STATUS 0x00010000 823 #define PCIEM_ROOT_STA_PME_PEND 0x00020000 824 #define PCIER_DEVICE_CAP2 0x24 825 #define PCIEM_CAP2_COMP_TIMO_RANGES 0x0000000f 826 #define PCIEM_CAP2_COMP_TIMO_RANGE_A 0x00000001 827 #define PCIEM_CAP2_COMP_TIMO_RANGE_B 0x00000002 828 #define PCIEM_CAP2_COMP_TIMO_RANGE_C 0x00000004 829 #define PCIEM_CAP2_COMP_TIMO_RANGE_D 0x00000008 830 #define PCIEM_CAP2_COMP_TIMO_DISABLE 0x00000010 831 #define PCIEM_CAP2_ARI 0x00000020 832 #define PCIER_DEVICE_CTL2 0x28 833 #define PCIEM_CTL2_COMP_TIMO_VAL 0x000f 834 #define PCIEM_CTL2_COMP_TIMO_50MS 0x0000 835 #define PCIEM_CTL2_COMP_TIMO_100US 0x0001 836 #define PCIEM_CTL2_COMP_TIMO_10MS 0x0002 837 #define PCIEM_CTL2_COMP_TIMO_55MS 0x0005 838 #define PCIEM_CTL2_COMP_TIMO_210MS 0x0006 839 #define PCIEM_CTL2_COMP_TIMO_900MS 0x0009 840 #define PCIEM_CTL2_COMP_TIMO_3500MS 0x000a 841 #define PCIEM_CTL2_COMP_TIMO_13S 0x000d 842 #define PCIEM_CTL2_COMP_TIMO_64S 0x000e 843 #define PCIEM_CTL2_COMP_TIMO_DISABLE 0x0010 844 #define PCIEM_CTL2_ARI 0x0020 845 #define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 846 #define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 847 #define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 848 #define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 849 #define PCIEM_CTL2_LTR_ENABLE 0x0400 850 #define PCIEM_CTL2_OBFF 0x6000 851 #define PCIEM_OBFF_DISABLE 0x0000 852 #define PCIEM_OBFF_MSGA_ENABLE 0x2000 853 #define PCIEM_OBFF_MSGB_ENABLE 0x4000 854 #define PCIEM_OBFF_WAKE_ENABLE 0x6000 855 #define PCIEM_CTL2_END2END_TLP 0x8000 856 #define PCIER_DEVICE_STA2 0x2a 857 #define PCIER_LINK_CAP2 0x2c 858 #define PCIER_LINK_CTL2 0x30 859 #define PCIER_LINK_STA2 0x32 860 #define PCIER_SLOT_CAP2 0x34 861 #define PCIER_SLOT_CTL2 0x38 862 #define PCIER_SLOT_STA2 0x3a 863 864 /* MSI-X definitions */ 865 #define PCIR_MSIX_CTRL 0x2 866 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 867 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 868 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 869 #define PCIR_MSIX_TABLE 0x4 870 #define PCIR_MSIX_PBA 0x8 871 #define PCIM_MSIX_BIR_MASK 0x7 872 #define PCIM_MSIX_BIR_BAR_10 0 873 #define PCIM_MSIX_BIR_BAR_14 1 874 #define PCIM_MSIX_BIR_BAR_18 2 875 #define PCIM_MSIX_BIR_BAR_1C 3 876 #define PCIM_MSIX_BIR_BAR_20 4 877 #define PCIM_MSIX_BIR_BAR_24 5 878 #define PCIM_MSIX_VCTRL_MASK 0x1 879 880 /* PCI Advanced Features definitions */ 881 #define PCIR_PCIAF_CAP 0x3 882 #define PCIM_PCIAFCAP_TP 0x01 883 #define PCIM_PCIAFCAP_FLR 0x02 884 #define PCIR_PCIAF_CTRL 0x4 885 #define PCIR_PCIAFCTRL_FLR 0x01 886 #define PCIR_PCIAF_STATUS 0x5 887 #define PCIR_PCIAFSTATUS_TP 0x01 888 889 /* Advanced Error Reporting */ 890 #define PCIR_AER_UC_STATUS 0x04 891 #define PCIM_AER_UC_TRAINING_ERROR 0x00000001 892 #define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 893 #define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020 894 #define PCIM_AER_UC_POISONED_TLP 0x00001000 895 #define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 896 #define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 897 #define PCIM_AER_UC_COMPLETER_ABORT 0x00008000 898 #define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000 899 #define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000 900 #define PCIM_AER_UC_MALFORMED_TLP 0x00040000 901 #define PCIM_AER_UC_ECRC_ERROR 0x00080000 902 #define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 903 #define PCIM_AER_UC_ACS_VIOLATION 0x00200000 904 #define PCIM_AER_UC_INTERNAL_ERROR 0x00400000 905 #define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000 906 #define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000 907 #define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000 908 #define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ 909 #define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ 910 #define PCIR_AER_COR_STATUS 0x10 911 #define PCIM_AER_COR_RECEIVER_ERROR 0x00000001 912 #define PCIM_AER_COR_BAD_TLP 0x00000040 913 #define PCIM_AER_COR_BAD_DLLP 0x00000080 914 #define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 915 #define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 916 #define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 917 #define PCIM_AER_COR_INTERNAL_ERROR 0x00004000 918 #define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000 919 #define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ 920 #define PCIR_AER_CAP_CONTROL 0x18 921 #define PCIM_AER_FIRST_ERROR_PTR 0x0000001f 922 #define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020 923 #define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 924 #define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 925 #define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 926 #define PCIM_AER_MULT_HDR_CAPABLE 0x00000200 927 #define PCIM_AER_MULT_HDR_ENABLE 0x00000400 928 #define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800 929 #define PCIR_AER_HEADER_LOG 0x1c 930 #define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ 931 #define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 932 #define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002 933 #define PCIM_AER_ROOTERR_F_ENABLE 0x00000004 934 #define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */ 935 #define PCIM_AER_ROOTERR_COR_ERR 0x00000001 936 #define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002 937 #define PCIM_AER_ROOTERR_UC_ERR 0x00000004 938 #define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008 939 #define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010 940 #define PCIM_AER_ROOTERR_NF_ERR 0x00000020 941 #define PCIM_AER_ROOTERR_F_ERR 0x00000040 942 #define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 943 #define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ 944 #define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ 945 #define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */ 946 947 /* Virtual Channel definitions */ 948 #define PCIR_VC_CAP1 0x04 949 #define PCIM_VC_CAP1_EXT_COUNT 0x00000007 950 #define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070 951 #define PCIR_VC_CAP2 0x08 952 #define PCIR_VC_CONTROL 0x0C 953 #define PCIR_VC_STATUS 0x0E 954 #define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C) 955 #define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C) 956 #define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C) 957 958 /* Serial Number definitions */ 959 #define PCIR_SERIAL_LOW 0x04 960 #define PCIR_SERIAL_HIGH 0x08 961 962