Searched refs:OP0 (Results 1 – 14 of 14) sorted by relevance
| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 846 SDValue OP0; in SelectMul() local 856 OP0 = Sext0; in SelectMul() 867 OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, in SelectMul() 903 OP0, OP1); in SelectMul() 1026 SDValue OP0; in SelectTruncate() local 1036 OP0 = Sext0; in SelectTruncate() 1047 OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, in SelectTruncate() 1082 OP0, OP1); in SelectTruncate()
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| /freebsd-10-stable/contrib/gcc/config/s390/ |
| D | s390.h | 744 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ argument 745 s390_canonicalize_comparison (&(CODE), &(OP0), &(OP1))
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| /freebsd-10-stable/contrib/gcc/config/arm/ |
| D | arm.h | 2148 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ argument 2156 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
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| D | arm.md | 6448 /* It's ok if OP0 is a lo-reg, even though the mov will set the
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| /freebsd-10-stable/contrib/gcc/ |
| D | tree.def | 938 If OFF > 0, the last VS - OFF elements of vector OP0 are concatenated to
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| D | ChangeLog-1999 | 1818 that is needed when OP0 is in a register. 3848 (expand_expr, case ARRAY_REF): If OP0 is in a register, put it in 13095 register instead of OP0.
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| D | FSFChangeLog.11 | 11145 * optabs.c (expand_abs): When OP0 and TARGET are the same
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| D | ChangeLog-2006 | 4200 (derive_constant_upper_bound): Handle OP0 - CST in unsigned types
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| D | ChangeLog.tree-ssa | 9904 make sure OP0 is a suitable constant before trying to fold it.
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| D | ChangeLog-2001 | 9601 (expand_expr, case COMPONENT_EXPR): Always copy OP0 when we need
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| D | ChangeLog-2003 | 14027 * expr.c (expand_expr, case COMPONENT_REF): If reg, copy OP0 to MEM
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| D | ChangeLog-2004 | 31876 turning off bits already known to be off in OP0.
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| /freebsd-10-stable/contrib/gcc/config/mips/ |
| D | mips.md | 1550 ;; OP5 <- LO, OP0 <- HI 1562 ;; Shift OP0 into place.
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| /freebsd-10-stable/contrib/binutils/bfd/ |
| D | ChangeLog-0203 | 3836 PLT,OP0,OP1,OP2,ASM_EXPAND,ASM_SIMPLIFY}.
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