Searched refs:MIPS_FPU_ENABLE_DIV0 (Results 1 – 2 of 2) sorted by relevance
610 #define MIPS_FPU_ENABLE_DIV0 0x00000400 macro
1082 and v0, a1, MIPS_FPU_ENABLE_DIV0 # trap enabled?1156 and v0, a1, MIPS_FPU_ENABLE_DIV0 # trap enabled?