1 /*-
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
14 * distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: stable/10/sys/mips/nlm/hal/nae.h 255368 2013-09-07 18:26:16Z jchandra $
29 */
30
31 #ifndef __NLM_NAE_H__
32 #define __NLM_NAE_H__
33
34 /**
35 * @file_name nae.h
36 * @author Netlogic Microsystems
37 * @brief Basic definitions of XLP Networt Accelerator Engine
38 */
39
40 /* NAE specific registers */
41 #define NAE_REG(blk, intf, reg) (((blk) << 11) | ((intf) << 7) | (reg))
42
43 /* ingress path registers */
44 #define NAE_RX_CONFIG NAE_REG(7, 0, 0x10)
45 #define NAE_RX_IF_BASE_CONFIG0 NAE_REG(7, 0, 0x12)
46 #define NAE_RX_IF_BASE_CONFIG1 NAE_REG(7, 0, 0x13)
47 #define NAE_RX_IF_BASE_CONFIG2 NAE_REG(7, 0, 0x14)
48 #define NAE_RX_IF_BASE_CONFIG3 NAE_REG(7, 0, 0x15)
49 #define NAE_RX_IF_BASE_CONFIG4 NAE_REG(7, 0, 0x16)
50 #define NAE_RX_IF_BASE_CONFIG5 NAE_REG(7, 0, 0x17)
51 #define NAE_RX_IF_BASE_CONFIG6 NAE_REG(7, 0, 0x18)
52 #define NAE_RX_IF_BASE_CONFIG7 NAE_REG(7, 0, 0x19)
53 #define NAE_RX_IF_BASE_CONFIG8 NAE_REG(7, 0, 0x1a)
54 #define NAE_RX_IF_BASE_CONFIG9 NAE_REG(7, 0, 0x1b)
55 #define NAE_RX_IF_VEC_VALID NAE_REG(7, 0, 0x1c)
56 #define NAE_RX_IF_SLOT_CAL NAE_REG(7, 0, 0x1d)
57 #define NAE_PARSER_CONFIG NAE_REG(7, 0, 0x1e)
58 #define NAE_PARSER_SEQ_FIFO_CFG NAE_REG(7, 0, 0x1f)
59 #define NAE_FREE_IN_FIFO_CFG NAE_REG(7, 0, 0x20)
60 #define NAE_RXBUF_BASE_DPTH_ADDR NAE_REG(7, 0, 0x21)
61 #define NAE_RXBUF_BASE_DPTH NAE_REG(7, 0, 0x22)
62 #define NAE_RX_UCORE_CFG NAE_REG(7, 0, 0x23)
63 #define NAE_RX_UCORE_CAM_MASK0 NAE_REG(7, 0, 0x24)
64 #define NAE_RX_UCORE_CAM_MASK1 NAE_REG(7, 0, 0x25)
65 #define NAE_RX_UCORE_CAM_MASK2 NAE_REG(7, 0, 0x26)
66 #define NAE_RX_UCORE_CAM_MASK3 NAE_REG(7, 0, 0x27)
67 #define NAE_FREEIN_FIFO_UNIQ_SZ_CFG NAE_REG(7, 0, 0x28)
68 #define NAE_RX_CRC_POLY0_CFG NAE_REG(7, 0, 0x2a)
69 #define NAE_RX_CRC_POLY1_CFG NAE_REG(7, 0, 0x2b)
70 #define NAE_FREE_SPILL0_MEM_CFG NAE_REG(7, 0, 0x2c)
71 #define NAE_FREE_SPILL1_MEM_CFG NAE_REG(7, 0, 0x2d)
72 #define NAE_FREEFIFO_THRESH_CFG NAE_REG(7, 0, 0x2e)
73 #define NAE_FLOW_CRC16_POLY_CFG NAE_REG(7, 0, 0x2f)
74 #define NAE_EGR_NIOR_CAL_LEN_REG NAE_REG(7, 0, 0x4e)
75 #define NAE_EGR_NIOR_CRDT_CAL_PROG NAE_REG(7, 0, 0x52)
76 #define NAE_TEST NAE_REG(7, 0, 0x5f)
77 #define NAE_BIU_TIMEOUT_CFG NAE_REG(7, 0, 0x60)
78 #define NAE_BIU_CFG NAE_REG(7, 0, 0x61)
79 #define NAE_RX_FREE_FIFO_POP NAE_REG(7, 0, 0x62)
80 #define NAE_RX_DSBL_ECC NAE_REG(7, 0, 0x63)
81 #define NAE_FLOW_BASEMASK_CFG NAE_REG(7, 0, 0x80)
82 #define NAE_POE_CLASS_SETUP_CFG NAE_REG(7, 0, 0x81)
83 #define NAE_UCORE_IFACEMASK_CFG NAE_REG(7, 0, 0x82)
84 #define NAE_RXBUF_XOFFON_THRESH NAE_REG(7, 0, 0x83)
85 #define NAE_FLOW_TABLE1_CFG NAE_REG(7, 0, 0x84)
86 #define NAE_FLOW_TABLE2_CFG NAE_REG(7, 0, 0x85)
87 #define NAE_FLOW_TABLE3_CFG NAE_REG(7, 0, 0x86)
88 #define NAE_RX_FREE_FIFO_THRESH NAE_REG(7, 0, 0x87)
89 #define NAE_RX_PARSER_UNCLA NAE_REG(7, 0, 0x88)
90 #define NAE_RX_BUF_INTR_THRESH NAE_REG(7, 0, 0x89)
91 #define NAE_IFACE_FIFO_CFG NAE_REG(7, 0, 0x8a)
92 #define NAE_PARSER_SEQ_FIFO_THRESH_CFG NAE_REG(7, 0, 0x8b)
93 #define NAE_RX_ERRINJ_CTRL0 NAE_REG(7, 0, 0x8c)
94 #define NAE_RX_ERRINJ_CTRL1 NAE_REG(7, 0, 0x8d)
95 #define NAE_RX_ERR_LATCH0 NAE_REG(7, 0, 0x8e)
96 #define NAE_RX_ERR_LATCH1 NAE_REG(7, 0, 0x8f)
97 #define NAE_RX_PERF_CTR_CFG NAE_REG(7, 0, 0xa0)
98 #define NAE_RX_PERF_CTR_VAL NAE_REG(7, 0, 0xa1)
99
100 /* NAE hardware parser registers */
101 #define NAE_L2_TYPE_PORT0 NAE_REG(7, 0, 0x210)
102 #define NAE_L2_TYPE_PORT1 NAE_REG(7, 0, 0x211)
103 #define NAE_L2_TYPE_PORT2 NAE_REG(7, 0, 0x212)
104 #define NAE_L2_TYPE_PORT3 NAE_REG(7, 0, 0x213)
105 #define NAE_L2_TYPE_PORT4 NAE_REG(7, 0, 0x214)
106 #define NAE_L2_TYPE_PORT5 NAE_REG(7, 0, 0x215)
107 #define NAE_L2_TYPE_PORT6 NAE_REG(7, 0, 0x216)
108 #define NAE_L2_TYPE_PORT7 NAE_REG(7, 0, 0x217)
109 #define NAE_L2_TYPE_PORT8 NAE_REG(7, 0, 0x218)
110 #define NAE_L2_TYPE_PORT9 NAE_REG(7, 0, 0x219)
111 #define NAE_L2_TYPE_PORT10 NAE_REG(7, 0, 0x21a)
112 #define NAE_L2_TYPE_PORT11 NAE_REG(7, 0, 0x21b)
113 #define NAE_L2_TYPE_PORT12 NAE_REG(7, 0, 0x21c)
114 #define NAE_L2_TYPE_PORT13 NAE_REG(7, 0, 0x21d)
115 #define NAE_L2_TYPE_PORT14 NAE_REG(7, 0, 0x21e)
116 #define NAE_L2_TYPE_PORT15 NAE_REG(7, 0, 0x21f)
117 #define NAE_L2_TYPE_PORT16 NAE_REG(7, 0, 0x220)
118 #define NAE_L2_TYPE_PORT17 NAE_REG(7, 0, 0x221)
119 #define NAE_L2_TYPE_PORT18 NAE_REG(7, 0, 0x222)
120 #define NAE_L2_TYPE_PORT19 NAE_REG(7, 0, 0x223)
121 #define NAE_L3_CTABLE_MASK0 NAE_REG(7, 0, 0x22c)
122 #define NAE_L3_CTABLE_MASK1 NAE_REG(7, 0, 0x22d)
123 #define NAE_L3_CTABLE_MASK2 NAE_REG(7, 0, 0x22e)
124 #define NAE_L3_CTABLE_MASK3 NAE_REG(7, 0, 0x22f)
125 #define NAE_L3CTABLE0 NAE_REG(7, 0, 0x230)
126 #define NAE_L3CTABLE1 NAE_REG(7, 0, 0x231)
127 #define NAE_L3CTABLE2 NAE_REG(7, 0, 0x232)
128 #define NAE_L3CTABLE3 NAE_REG(7, 0, 0x233)
129 #define NAE_L3CTABLE4 NAE_REG(7, 0, 0x234)
130 #define NAE_L3CTABLE5 NAE_REG(7, 0, 0x235)
131 #define NAE_L3CTABLE6 NAE_REG(7, 0, 0x236)
132 #define NAE_L3CTABLE7 NAE_REG(7, 0, 0x237)
133 #define NAE_L3CTABLE8 NAE_REG(7, 0, 0x238)
134 #define NAE_L3CTABLE9 NAE_REG(7, 0, 0x239)
135 #define NAE_L3CTABLE10 NAE_REG(7, 0, 0x23a)
136 #define NAE_L3CTABLE11 NAE_REG(7, 0, 0x23b)
137 #define NAE_L3CTABLE12 NAE_REG(7, 0, 0x23c)
138 #define NAE_L3CTABLE13 NAE_REG(7, 0, 0x23d)
139 #define NAE_L3CTABLE14 NAE_REG(7, 0, 0x23e)
140 #define NAE_L3CTABLE15 NAE_REG(7, 0, 0x23f)
141 #define NAE_L4CTABLE0 NAE_REG(7, 0, 0x250)
142 #define NAE_L4CTABLE1 NAE_REG(7, 0, 0x251)
143 #define NAE_L4CTABLE2 NAE_REG(7, 0, 0x252)
144 #define NAE_L4CTABLE3 NAE_REG(7, 0, 0x253)
145 #define NAE_L4CTABLE4 NAE_REG(7, 0, 0x254)
146 #define NAE_L4CTABLE5 NAE_REG(7, 0, 0x255)
147 #define NAE_L4CTABLE6 NAE_REG(7, 0, 0x256)
148 #define NAE_L4CTABLE7 NAE_REG(7, 0, 0x257)
149 #define NAE_IPV6_EXT_HEADER0 NAE_REG(7, 0, 0x260)
150 #define NAE_IPV6_EXT_HEADER1 NAE_REG(7, 0, 0x261)
151 #define NAE_VLAN_TYPES01 NAE_REG(7, 0, 0x262)
152 #define NAE_VLAN_TYPES23 NAE_REG(7, 0, 0x263)
153
154 /* NAE Egress path registers */
155 #define NAE_TX_CONFIG NAE_REG(7, 0, 0x11)
156 #define NAE_DMA_TX_CREDIT_TH NAE_REG(7, 0, 0x29)
157 #define NAE_STG1_STG2CRDT_CMD NAE_REG(7, 0, 0x30)
158 #define NAE_STG2_EHCRDT_CMD NAE_REG(7, 0, 0x32)
159 #define NAE_EH_FREECRDT_CMD NAE_REG(7, 0, 0x34)
160 #define NAE_STG2_STRCRDT_CMD NAE_REG(7, 0, 0x36)
161 #define NAE_TXFIFO_IFACEMAP_CMD NAE_REG(7, 0, 0x38)
162 #define NAE_VFBID_DESTMAP_CMD NAE_REG(7, 0, 0x3a)
163 #define NAE_STG1_PMEM_PROG NAE_REG(7, 0, 0x3c)
164 #define NAE_STG2_PMEM_PROG NAE_REG(7, 0, 0x3e)
165 #define NAE_EH_PMEM_PROG NAE_REG(7, 0, 0x40)
166 #define NAE_FREE_PMEM_PROG NAE_REG(7, 0, 0x42)
167 #define NAE_TX_DDR_ACTVLIST_CMD NAE_REG(7, 0, 0x44)
168 #define NAE_TX_IF_BURSTMAX_CMD NAE_REG(7, 0, 0x46)
169 #define NAE_TX_IF_ENABLE_CMD NAE_REG(7, 0, 0x48)
170 #define NAE_TX_PKTLEN_PMEM_CMD NAE_REG(7, 0, 0x4a)
171 #define NAE_TX_SCHED_MAP_CMD0 NAE_REG(7, 0, 0x4c)
172 #define NAE_TX_SCHED_MAP_CMD1 NAE_REG(7, 0, 0x4d)
173 #define NAE_TX_PKT_PMEM_CMD0 NAE_REG(7, 0, 0x50)
174 #define NAE_TX_PKT_PMEM_CMD1 NAE_REG(7, 0, 0x51)
175 #define NAE_TX_SCHED_CTRL NAE_REG(7, 0, 0x53)
176 #define NAE_TX_CRC_POLY0 NAE_REG(7, 0, 0x54)
177 #define NAE_TX_CRC_POLY1 NAE_REG(7, 0, 0x55)
178 #define NAE_TX_CRC_POLY2 NAE_REG(7, 0, 0x56)
179 #define NAE_TX_CRC_POLY3 NAE_REG(7, 0, 0x57)
180 #define NAE_STR_PMEM_CMD NAE_REG(7, 0, 0x58)
181 #define NAE_TX_IORCRDT_INIT NAE_REG(7, 0, 0x59)
182 #define NAE_TX_DSBL_ECC NAE_REG(7, 0, 0x5a)
183 #define NAE_TX_IORCRDT_IGNORE NAE_REG(7, 0, 0x5b)
184 #define NAE_IF0_1588_TMSTMP_HI NAE_REG(7, 0, 0x300)
185 #define NAE_IF1_1588_TMSTMP_HI NAE_REG(7, 0, 0x302)
186 #define NAE_IF2_1588_TMSTMP_HI NAE_REG(7, 0, 0x304)
187 #define NAE_IF3_1588_TMSTMP_HI NAE_REG(7, 0, 0x306)
188 #define NAE_IF4_1588_TMSTMP_HI NAE_REG(7, 0, 0x308)
189 #define NAE_IF5_1588_TMSTMP_HI NAE_REG(7, 0, 0x30a)
190 #define NAE_IF6_1588_TMSTMP_HI NAE_REG(7, 0, 0x30c)
191 #define NAE_IF7_1588_TMSTMP_HI NAE_REG(7, 0, 0x30e)
192 #define NAE_IF8_1588_TMSTMP_HI NAE_REG(7, 0, 0x310)
193 #define NAE_IF9_1588_TMSTMP_HI NAE_REG(7, 0, 0x312)
194 #define NAE_IF10_1588_TMSTMP_HI NAE_REG(7, 0, 0x314)
195 #define NAE_IF11_1588_TMSTMP_HI NAE_REG(7, 0, 0x316)
196 #define NAE_IF12_1588_TMSTMP_HI NAE_REG(7, 0, 0x318)
197 #define NAE_IF13_1588_TMSTMP_HI NAE_REG(7, 0, 0x31a)
198 #define NAE_IF14_1588_TMSTMP_HI NAE_REG(7, 0, 0x31c)
199 #define NAE_IF15_1588_TMSTMP_HI NAE_REG(7, 0, 0x31e)
200 #define NAE_IF16_1588_TMSTMP_HI NAE_REG(7, 0, 0x320)
201 #define NAE_IF17_1588_TMSTMP_HI NAE_REG(7, 0, 0x322)
202 #define NAE_IF18_1588_TMSTMP_HI NAE_REG(7, 0, 0x324)
203 #define NAE_IF19_1588_TMSTMP_HI NAE_REG(7, 0, 0x326)
204 #define NAE_IF0_1588_TMSTMP_LO NAE_REG(7, 0, 0x301)
205 #define NAE_IF1_1588_TMSTMP_LO NAE_REG(7, 0, 0x303)
206 #define NAE_IF2_1588_TMSTMP_LO NAE_REG(7, 0, 0x305)
207 #define NAE_IF3_1588_TMSTMP_LO NAE_REG(7, 0, 0x307)
208 #define NAE_IF4_1588_TMSTMP_LO NAE_REG(7, 0, 0x309)
209 #define NAE_IF5_1588_TMSTMP_LO NAE_REG(7, 0, 0x30b)
210 #define NAE_IF6_1588_TMSTMP_LO NAE_REG(7, 0, 0x30d)
211 #define NAE_IF7_1588_TMSTMP_LO NAE_REG(7, 0, 0x30f)
212 #define NAE_IF8_1588_TMSTMP_LO NAE_REG(7, 0, 0x311)
213 #define NAE_IF9_1588_TMSTMP_LO NAE_REG(7, 0, 0x313)
214 #define NAE_IF10_1588_TMSTMP_LO NAE_REG(7, 0, 0x315)
215 #define NAE_IF11_1588_TMSTMP_LO NAE_REG(7, 0, 0x317)
216 #define NAE_IF12_1588_TMSTMP_LO NAE_REG(7, 0, 0x319)
217 #define NAE_IF13_1588_TMSTMP_LO NAE_REG(7, 0, 0x31b)
218 #define NAE_IF14_1588_TMSTMP_LO NAE_REG(7, 0, 0x31d)
219 #define NAE_IF15_1588_TMSTMP_LO NAE_REG(7, 0, 0x31f)
220 #define NAE_IF16_1588_TMSTMP_LO NAE_REG(7, 0, 0x321)
221 #define NAE_IF17_1588_TMSTMP_LO NAE_REG(7, 0, 0x323)
222 #define NAE_IF18_1588_TMSTMP_LO NAE_REG(7, 0, 0x325)
223 #define NAE_IF19_1588_TMSTMP_LO NAE_REG(7, 0, 0x327)
224 #define NAE_TX_EL0 NAE_REG(7, 0, 0x328)
225 #define NAE_TX_EL1 NAE_REG(7, 0, 0x329)
226 #define NAE_EIC0 NAE_REG(7, 0, 0x32a)
227 #define NAE_EIC1 NAE_REG(7, 0, 0x32b)
228 #define NAE_STG1_STG2CRDT_STATUS NAE_REG(7, 0, 0x32c)
229 #define NAE_STG2_EHCRDT_STATUS NAE_REG(7, 0, 0x32d)
230 #define NAE_STG2_FREECRDT_STATUS NAE_REG(7, 0, 0x32e)
231 #define NAE_STG2_STRCRDT_STATUS NAE_REG(7, 0, 0x32f)
232 #define NAE_TX_PERF_CNTR_INTR_STATUS NAE_REG(7, 0, 0x330)
233 #define NAE_TX_PERF_CNTR_ROLL_STATUS NAE_REG(7, 0, 0x331)
234 #define NAE_TX_PERF_CNTR0 NAE_REG(7, 0, 0x332)
235 #define NAE_TX_PERF_CNTR1 NAE_REG(7, 0, 0x334)
236 #define NAE_TX_PERF_CNTR2 NAE_REG(7, 0, 0x336)
237 #define NAE_TX_PERF_CNTR3 NAE_REG(7, 0, 0x338)
238 #define NAE_TX_PERF_CNTR4 NAE_REG(7, 0, 0x33a)
239 #define NAE_TX_PERF_CNTR0_CTL NAE_REG(7, 0, 0x333)
240 #define NAE_TX_PERF_CNTR1_CTL NAE_REG(7, 0, 0x335)
241 #define NAE_TX_PERF_CNTR2_CTL NAE_REG(7, 0, 0x337)
242 #define NAE_TX_PERF_CNTR3_CTL NAE_REG(7, 0, 0x339)
243 #define NAE_TX_PERF_CNTR4_CTL NAE_REG(7, 0, 0x33b)
244 #define NAE_VFBID_DESTMAP_STATUS NAE_REG(7, 0, 0x380)
245 #define NAE_STG2_PMEM_STATUS NAE_REG(7, 0, 0x381)
246 #define NAE_EH_PMEM_STATUS NAE_REG(7, 0, 0x382)
247 #define NAE_FREE_PMEM_STATUS NAE_REG(7, 0, 0x383)
248 #define NAE_TX_DDR_ACTVLIST_STATUS NAE_REG(7, 0, 0x384)
249 #define NAE_TX_IF_BURSTMAX_STATUS NAE_REG(7, 0, 0x385)
250 #define NAE_TX_PKTLEN_PMEM_STATUS NAE_REG(7, 0, 0x386)
251 #define NAE_TX_SCHED_MAP_STATUS0 NAE_REG(7, 0, 0x387)
252 #define NAE_TX_SCHED_MAP_STATUS1 NAE_REG(7, 0, 0x388)
253 #define NAE_TX_PKT_PMEM_STATUS NAE_REG(7, 0, 0x389)
254 #define NAE_STR_PMEM_STATUS NAE_REG(7, 0, 0x38a)
255
256 /* Network interface interrupt registers */
257 #define NAE_NET_IF0_INTR_STAT NAE_REG(7, 0, 0x280)
258 #define NAE_NET_IF1_INTR_STAT NAE_REG(7, 0, 0x282)
259 #define NAE_NET_IF2_INTR_STAT NAE_REG(7, 0, 0x284)
260 #define NAE_NET_IF3_INTR_STAT NAE_REG(7, 0, 0x286)
261 #define NAE_NET_IF4_INTR_STAT NAE_REG(7, 0, 0x288)
262 #define NAE_NET_IF5_INTR_STAT NAE_REG(7, 0, 0x28a)
263 #define NAE_NET_IF6_INTR_STAT NAE_REG(7, 0, 0x28c)
264 #define NAE_NET_IF7_INTR_STAT NAE_REG(7, 0, 0x28e)
265 #define NAE_NET_IF8_INTR_STAT NAE_REG(7, 0, 0x290)
266 #define NAE_NET_IF9_INTR_STAT NAE_REG(7, 0, 0x292)
267 #define NAE_NET_IF10_INTR_STAT NAE_REG(7, 0, 0x294)
268 #define NAE_NET_IF11_INTR_STAT NAE_REG(7, 0, 0x296)
269 #define NAE_NET_IF12_INTR_STAT NAE_REG(7, 0, 0x298)
270 #define NAE_NET_IF13_INTR_STAT NAE_REG(7, 0, 0x29a)
271 #define NAE_NET_IF14_INTR_STAT NAE_REG(7, 0, 0x29c)
272 #define NAE_NET_IF15_INTR_STAT NAE_REG(7, 0, 0x29e)
273 #define NAE_NET_IF16_INTR_STAT NAE_REG(7, 0, 0x2a0)
274 #define NAE_NET_IF17_INTR_STAT NAE_REG(7, 0, 0x2a2)
275 #define NAE_NET_IF18_INTR_STAT NAE_REG(7, 0, 0x2a4)
276 #define NAE_NET_IF19_INTR_STAT NAE_REG(7, 0, 0x2a6)
277 #define NAE_NET_IF0_INTR_MASK NAE_REG(7, 0, 0x281)
278 #define NAE_NET_IF1_INTR_MASK NAE_REG(7, 0, 0x283)
279 #define NAE_NET_IF2_INTR_MASK NAE_REG(7, 0, 0x285)
280 #define NAE_NET_IF3_INTR_MASK NAE_REG(7, 0, 0x287)
281 #define NAE_NET_IF4_INTR_MASK NAE_REG(7, 0, 0x289)
282 #define NAE_NET_IF5_INTR_MASK NAE_REG(7, 0, 0x28b)
283 #define NAE_NET_IF6_INTR_MASK NAE_REG(7, 0, 0x28d)
284 #define NAE_NET_IF7_INTR_MASK NAE_REG(7, 0, 0x28f)
285 #define NAE_NET_IF8_INTR_MASK NAE_REG(7, 0, 0x291)
286 #define NAE_NET_IF9_INTR_MASK NAE_REG(7, 0, 0x293)
287 #define NAE_NET_IF10_INTR_MASK NAE_REG(7, 0, 0x295)
288 #define NAE_NET_IF11_INTR_MASK NAE_REG(7, 0, 0x297)
289 #define NAE_NET_IF12_INTR_MASK NAE_REG(7, 0, 0x299)
290 #define NAE_NET_IF13_INTR_MASK NAE_REG(7, 0, 0x29b)
291 #define NAE_NET_IF14_INTR_MASK NAE_REG(7, 0, 0x29d)
292 #define NAE_NET_IF15_INTR_MASK NAE_REG(7, 0, 0x29f)
293 #define NAE_NET_IF16_INTR_MASK NAE_REG(7, 0, 0x2a1)
294 #define NAE_NET_IF17_INTR_MASK NAE_REG(7, 0, 0x2a3)
295 #define NAE_NET_IF18_INTR_MASK NAE_REG(7, 0, 0x2a5)
296 #define NAE_NET_IF19_INTR_MASK NAE_REG(7, 0, 0x2a7)
297 #define NAE_COMMON0_INTR_STAT NAE_REG(7, 0, 0x2a8)
298 #define NAE_COMMON0_INTR_MASK NAE_REG(7, 0, 0x2a9)
299 #define NAE_COMMON1_INTR_STAT NAE_REG(7, 0, 0x2aa)
300 #define NAE_COMMON1_INTR_MASK NAE_REG(7, 0, 0x2ab)
301
302 /* Network Interface Low-block Registers */
303 #define NAE_PHY_LANE0_STATUS(block) NAE_REG(block, 0xe, 0)
304 #define NAE_PHY_LANE1_STATUS(block) NAE_REG(block, 0xe, 1)
305 #define NAE_PHY_LANE2_STATUS(block) NAE_REG(block, 0xe, 2)
306 #define NAE_PHY_LANE3_STATUS(block) NAE_REG(block, 0xe, 3)
307 #define NAE_PHY_LANE0_CTRL(block) NAE_REG(block, 0xe, 4)
308 #define NAE_PHY_LANE1_CTRL(block) NAE_REG(block, 0xe, 5)
309 #define NAE_PHY_LANE2_CTRL(block) NAE_REG(block, 0xe, 6)
310 #define NAE_PHY_LANE3_CTRL(block) NAE_REG(block, 0xe, 7)
311
312 /* Network interface Top-block registers */
313 #define NAE_LANE_CFG_CPLX_0_1 NAE_REG(7, 0, 0x780)
314 #define NAE_LANE_CFG_CPLX_2_3 NAE_REG(7, 0, 0x781)
315 #define NAE_LANE_CFG_CPLX_4 NAE_REG(7, 0, 0x782)
316 #define NAE_LANE_CFG_SOFTRESET NAE_REG(7, 0, 0x783)
317 #define NAE_1588_PTP_OFFSET_HI NAE_REG(7, 0, 0x784)
318 #define NAE_1588_PTP_OFFSET_LO NAE_REG(7, 0, 0x785)
319 #define NAE_1588_PTP_INC_DEN NAE_REG(7, 0, 0x786)
320 #define NAE_1588_PTP_INC_NUM NAE_REG(7, 0, 0x787)
321 #define NAE_1588_PTP_INC_INTG NAE_REG(7, 0, 0x788)
322 #define NAE_1588_PTP_CONTROL NAE_REG(7, 0, 0x789)
323 #define NAE_1588_PTP_STATUS NAE_REG(7, 0, 0x78a)
324 #define NAE_1588_PTP_USER_VALUE_HI NAE_REG(7, 0, 0x78b)
325 #define NAE_1588_PTP_USER_VALUE_LO NAE_REG(7, 0, 0x78c)
326 #define NAE_1588_PTP_TMR1_HI NAE_REG(7, 0, 0x78d)
327 #define NAE_1588_PTP_TMR1_LO NAE_REG(7, 0, 0x78e)
328 #define NAE_1588_PTP_TMR2_HI NAE_REG(7, 0, 0x78f)
329 #define NAE_1588_PTP_TMR2_LO NAE_REG(7, 0, 0x790)
330 #define NAE_1588_PTP_TMR3_HI NAE_REG(7, 0, 0x791)
331 #define NAE_1588_PTP_TMR3_LO NAE_REG(7, 0, 0x792)
332 #define NAE_TX_FC_CAL_IDX_TBL_CTRL NAE_REG(7, 0, 0x793)
333 #define NAE_TX_FC_CAL_TBL_CTRL NAE_REG(7, 0, 0x794)
334 #define NAE_TX_FC_CAL_TBL_DATA0 NAE_REG(7, 0, 0x795)
335 #define NAE_TX_FC_CAL_TBL_DATA1 NAE_REG(7, 0, 0x796)
336 #define NAE_TX_FC_CAL_TBL_DATA2 NAE_REG(7, 0, 0x797)
337 #define NAE_TX_FC_CAL_TBL_DATA3 NAE_REG(7, 0, 0x798)
338 #define NAE_INT_MDIO_CTRL NAE_REG(7, 0, 0x799)
339 #define NAE_INT_MDIO_CTRL_DATA NAE_REG(7, 0, 0x79a)
340 #define NAE_INT_MDIO_RD_STAT NAE_REG(7, 0, 0x79b)
341 #define NAE_INT_MDIO_LINK_STAT NAE_REG(7, 0, 0x79c)
342 #define NAE_EXT_G0_MDIO_CTRL NAE_REG(7, 0, 0x79d)
343 #define NAE_EXT_G1_MDIO_CTRL NAE_REG(7, 0, 0x7a1)
344 #define NAE_EXT_G0_MDIO_CTRL_DATA NAE_REG(7, 0, 0x79e)
345 #define NAE_EXT_G1_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7a2)
346 #define NAE_EXT_G0_MDIO_RD_STAT NAE_REG(7, 0, 0x79f)
347 #define NAE_EXT_G1_MDIO_RD_STAT NAE_REG(7, 0, 0x7a3)
348 #define NAE_EXT_G0_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a0)
349 #define NAE_EXT_G1_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a4)
350 #define NAE_EXT_XG0_MDIO_CTRL NAE_REG(7, 0, 0x7a5)
351 #define NAE_EXT_XG1_MDIO_CTRL NAE_REG(7, 0, 0x7a9)
352 #define NAE_EXT_XG0_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7a6)
353 #define NAE_EXT_XG1_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7aa)
354 #define NAE_EXT_XG0_MDIO_RD_STAT NAE_REG(7, 0, 0x7a7)
355 #define NAE_EXT_XG1_MDIO_RD_STAT NAE_REG(7, 0, 0x7ab)
356 #define NAE_EXT_XG0_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a8)
357 #define NAE_EXT_XG1_MDIO_LINK_STAT NAE_REG(7, 0, 0x7ac)
358 #define NAE_GMAC_FC_SLOT0 NAE_REG(7, 0, 0x7ad)
359 #define NAE_GMAC_FC_SLOT1 NAE_REG(7, 0, 0x7ae)
360 #define NAE_GMAC_FC_SLOT2 NAE_REG(7, 0, 0x7af)
361 #define NAE_GMAC_FC_SLOT3 NAE_REG(7, 0, 0x7b0)
362 #define NAE_NETIOR_NTB_SLOT NAE_REG(7, 0, 0x7b1)
363 #define NAE_NETIOR_MISC_CTRL0 NAE_REG(7, 0, 0x7b2)
364 #define NAE_NETIOR_INT0 NAE_REG(7, 0, 0x7b3)
365 #define NAE_NETIOR_INT0_MASK NAE_REG(7, 0, 0x7b4)
366 #define NAE_NETIOR_INT1 NAE_REG(7, 0, 0x7b5)
367 #define NAE_NETIOR_INT1_MASK NAE_REG(7, 0, 0x7b6)
368 #define NAE_GMAC_PFC_REPEAT NAE_REG(7, 0, 0x7b7)
369 #define NAE_XGMAC_PFC_REPEAT NAE_REG(7, 0, 0x7b8)
370 #define NAE_NETIOR_MISC_CTRL1 NAE_REG(7, 0, 0x7b9)
371 #define NAE_NETIOR_MISC_CTRL2 NAE_REG(7, 0, 0x7ba)
372 #define NAE_NETIOR_INT2 NAE_REG(7, 0, 0x7bb)
373 #define NAE_NETIOR_INT2_MASK NAE_REG(7, 0, 0x7bc)
374 #define NAE_NETIOR_MISC_CTRL3 NAE_REG(7, 0, 0x7bd)
375
376 /* Network interface lane configuration registers */
377 #define NAE_LANE_CFG_MISCREG1 NAE_REG(7, 0xf, 0x39)
378 #define NAE_LANE_CFG_MISCREG2 NAE_REG(7, 0xf, 0x3A)
379
380 /* Network interface soft reset register */
381 #define NAE_SOFT_RESET NAE_REG(7, 0xf, 3)
382
383 /* ucore instruction/shared CAM RAM access */
384 #define NAE_UCORE_SHARED_RAM_OFFSET 0x10000
385
386 #define PORTS_PER_CMPLX 4
387 #define NAE_CACHELINE_SIZE 64
388
389 #define PHY_LANE_0_CTRL 4
390 #define PHY_LANE_1_CTRL 5
391 #define PHY_LANE_2_CTRL 6
392 #define PHY_LANE_3_CTRL 7
393
394 #define PHY_LANE_STAT_SRCS 0x00000001
395 #define PHY_LANE_STAT_STD 0x00000010
396 #define PHY_LANE_STAT_SFEA 0x00000020
397 #define PHY_LANE_STAT_STCS 0x00000040
398 #define PHY_LANE_STAT_SPC 0x00000200
399 #define PHY_LANE_STAT_XLF 0x00000400
400 #define PHY_LANE_STAT_PCR 0x00000800
401
402 #define PHY_LANE_CTRL_DATA_POS 0
403 #define PHY_LANE_CTRL_ADDR_POS 8
404 #define PHY_LANE_CTRL_CMD_READ 0x00010000
405 #define PHY_LANE_CTRL_CMD_WRITE 0x00000000
406 #define PHY_LANE_CTRL_CMD_START 0x00020000
407 #define PHY_LANE_CTRL_CMD_PENDING 0x00040000
408 #define PHY_LANE_CTRL_ALL 0x00200000
409 #define PHY_LANE_CTRL_FAST_INIT 0x00400000
410 #define PHY_LANE_CTRL_REXSEL_POS 23
411 #define PHY_LANE_CTRL_PHYMODE_POS 25
412 #define PHY_LANE_CTRL_PWRDOWN 0x20000000
413 #define PHY_LANE_CTRL_RST 0x40000000
414 #define PHY_LANE_CTRL_RST_XAUI 0xc0000000
415 #define PHY_LANE_CTRL_BPC_XAUI 0x80000000
416
417 #define LANE_CFG_CPLX_0_1 0x0
418 #define LANE_CFG_CPLX_2_3 0x1
419 #define LANE_CFG_CPLX_4 0x2
420
421 #define MAC_CONF1 0x0
422 #define MAC_CONF2 0x1
423 #define MAX_FRM 0x4
424
425 #define NETIOR_GMAC_CTRL1 0x7F
426 #define NETIOR_GMAC_CTRL2 0x7E
427 #define NETIOR_GMAC_CTRL3 0x7C
428
429 #define SGMII_CAL_SLOTS 3
430 #define XAUI_CAL_SLOTS 13
431 #define IL8_CAL_SLOTS 26
432 #define IL4_CAL_SLOTS 10
433
434 #define NAE_DRR_QUANTA 2048
435
436 #define XLP3XX_STG2_FIFO_SZ 512
437 #define XLP3XX_EH_FIFO_SZ 512
438 #define XLP3XX_FROUT_FIFO_SZ 512
439 #define XLP3XX_MS_FIFO_SZ 512
440 #define XLP3XX_PKT_FIFO_SZ 8192
441 #define XLP3XX_PKTLEN_FIFO_SZ 512
442
443 #define XLP3XX_MAX_STG2_OFFSET 0x7F
444 #define XLP3XX_MAX_EH_OFFSET 0x1f
445 #define XLP3XX_MAX_FREE_OUT_OFFSET 0x1f
446 #define XLP3XX_MAX_MS_OFFSET 0xF
447 #define XLP3XX_MAX_PMEM_OFFSET 0x7FE
448
449 #define XLP3XX_STG1_2_CREDIT XLP3XX_STG2_FIFO_SZ
450 #define XLP3XX_STG2_EH_CREDIT XLP3XX_EH_FIFO_SZ
451 #define XLP3XX_STG2_FROUT_CREDIT XLP3XX_FROUT_FIFO_SZ
452 #define XLP3XX_STG2_MS_CREDIT XLP3XX_MS_FIFO_SZ
453
454 #define XLP8XX_STG2_FIFO_SZ 2048
455 #define XLP8XX_EH_FIFO_SZ 4096
456 #define XLP8XX_FROUT_FIFO_SZ 4096
457 #define XLP8XX_MS_FIFO_SZ 2048
458 #define XLP8XX_PKT_FIFO_SZ 16384
459 #define XLP8XX_PKTLEN_FIFO_SZ 2048
460
461 #define XLP8XX_MAX_STG2_OFFSET 0x7F
462 #define XLP8XX_MAX_EH_OFFSET 0x7F
463 #define XLP8XX_MAX_FREE_OUT_OFFSET 0x7F
464 #define XLP8XX_MAX_MS_OFFSET 0x1F
465 #define XLP8XX_MAX_PMEM_OFFSET 0x7FE
466
467 #define XLP8XX_STG1_2_CREDIT XLP8XX_STG2_FIFO_SZ
468 #define XLP8XX_STG2_EH_CREDIT XLP8XX_EH_FIFO_SZ
469 #define XLP8XX_STG2_FROUT_CREDIT XLP8XX_FROUT_FIFO_SZ
470 #define XLP8XX_STG2_MS_CREDIT XLP8XX_MS_FIFO_SZ
471
472 #define MAX_CAL_SLOTS 64
473 #define XLP_MAX_PORTS 18
474 #define XLP_STORM_MAX_PORTS 8
475
476 #define MAX_FREE_FIFO_POOL_8XX 20
477 #define MAX_FREE_FIFO_POOL_3XX 9
478
479 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
480
481 #define nlm_read_nae_reg(b, r) nlm_read_reg_xkphys(b, r)
482 #define nlm_write_nae_reg(b, r, v) nlm_write_reg_xkphys(b, r, v)
483 #define nlm_get_nae_pcibase(node) \
484 nlm_pcicfg_base(XLP_IO_NAE_OFFSET(node))
485 #define nlm_get_nae_regbase(node) \
486 nlm_xkphys_map_pcibar0(nlm_get_nae_pcibase(node))
487
488 #define MAX_POE_CLASSES 8
489 #define MAX_POE_CLASS_CTXT_TBL_SZ ((NUM_CONTEXTS / MAX_POE_CLASSES) + 1)
490 #define TXINITIORCR(x) (((x) & 0x7ffff) << 8)
491
492 enum XLPNAE_TX_TYPE {
493 P2D_NEOP = 0,
494 P2P,
495 P2D_EOP,
496 MSC
497 };
498
499 enum nblock_type {
500 UNKNOWN = 0, /* DONT MAKE IT NON-ZERO */
501 SGMIIC = 1,
502 XAUIC = 2,
503 ILC = 3
504 };
505
506 enum nae_interface_type {
507 GMAC_0 = 0,
508 GMAC_1,
509 GMAC_2,
510 GMAC_3,
511 XGMAC,
512 INTERLAKEN,
513 PHY = 0xE,
514 LANE_CFG = 0xF,
515 };
516
517 enum {
518 LM_UNCONNECTED = 0,
519 LM_SGMII = 1,
520 LM_XAUI = 2,
521 LM_IL = 3,
522 };
523
524 enum nae_block {
525 BLOCK_0 = 0,
526 BLOCK_1,
527 BLOCK_2,
528 BLOCK_3,
529 BLOCK_4,
530 BLOCK_5,
531 BLOCK_6,
532 BLOCK_7,
533 };
534
535 enum {
536 PHYMODE_NONE = 0,
537 PHYMODE_HS_SGMII = 1,
538 PHYMODE_XAUI = 1,
539 PHYMODE_SGMII = 2,
540 PHYMODE_IL = 3,
541 };
542
543 static __inline int
nae_num_complex(uint64_t nae_pcibase)544 nae_num_complex(uint64_t nae_pcibase)
545 {
546 return (nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG0) & 0xff);
547 }
548
549 static __inline int
nae_num_context(uint64_t nae_pcibase)550 nae_num_context(uint64_t nae_pcibase)
551 {
552 return (nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG5));
553 }
554
555 /* per port config structure */
556 struct nae_port_config {
557 int node; /* node id (quickread) */
558 int block; /* network block id (quickread) */
559 int port; /* port id - among the 18 in XLP */
560 int type; /* port type - see xlp_gmac_port_types */
561 int mdio_bus;
562 int phy_addr;
563 int num_channels;
564 int num_free_descs;
565 int free_desc_sizes;
566 int ucore_mask;
567 int loopback_mode; /* is complex is in loopback? */
568 uint32_t freein_spill_size; /* Freein spill size for each port */
569 uint32_t free_fifo_size; /* (512entries x 2desc/entry)1024desc */
570 uint32_t iface_fifo_size;/* 256 entries x 64B/entry = 16KB */
571 uint32_t pseq_fifo_size; /* 1024 entries - 1 pktlen/entry */
572 uint32_t rxbuf_size; /* 4096 entries x 64B = 256KB */
573 uint32_t rx_if_base_config;
574 uint32_t rx_slots_reqd;
575 uint32_t tx_slots_reqd;
576 uint32_t stg2_fifo_size;
577 uint32_t eh_fifo_size;
578 uint32_t frout_fifo_size;
579 uint32_t ms_fifo_size;
580 uint32_t pkt_fifo_size;
581 uint32_t pktlen_fifo_size;
582 uint32_t max_stg2_offset;
583 uint32_t max_eh_offset;
584 uint32_t max_frout_offset;
585 uint32_t max_ms_offset;
586 uint32_t max_pmem_offset;
587 uint32_t stg1_2_credit;
588 uint32_t stg2_eh_credit;
589 uint32_t stg2_frout_credit;
590 uint32_t stg2_ms_credit;
591 uint32_t vlan_pri_en;
592 uint32_t txq;
593 uint32_t rxfreeq;
594 uint32_t ieee1588_inc_intg;
595 uint32_t ieee1588_inc_den;
596 uint32_t ieee1588_inc_num;
597 uint64_t ieee1588_userval;
598 uint64_t ieee1588_ptpoff;
599 uint64_t ieee1588_tmr1;
600 uint64_t ieee1588_tmr2;
601 uint64_t ieee1588_tmr3;
602 };
603
604 void nlm_nae_flush_free_fifo(uint64_t nae_base, int nblocks);
605 void nlm_program_nae_parser_seq_fifo(uint64_t, int, struct nae_port_config *);
606 void nlm_setup_rx_cal_cfg(uint64_t, int, struct nae_port_config *);
607 void nlm_setup_tx_cal_cfg(uint64_t, int, struct nae_port_config *cfg);
608 void nlm_deflate_frin_fifo_carving(uint64_t, int);
609 void nlm_reset_nae(int);
610 int nlm_set_nae_frequency(int, int);
611 void nlm_setup_poe_class_config(uint64_t nae_base, int max_poe_classes,
612 int num_contexts, int *poe_cl_tbl);
613 void nlm_setup_vfbid_mapping(uint64_t);
614 void nlm_setup_flow_crc_poly(uint64_t, uint32_t);
615 void nlm_setup_iface_fifo_cfg(uint64_t, int, struct nae_port_config *);
616 void nlm_setup_rx_base_config(uint64_t, int, struct nae_port_config *);
617 void nlm_setup_rx_buf_config(uint64_t, int, struct nae_port_config *);
618 void nlm_setup_freein_fifo_cfg(uint64_t, struct nae_port_config *);
619 int nlm_get_flow_mask(int);
620 void nlm_program_flow_cfg(uint64_t, int, uint32_t, uint32_t);
621 void xlp_ax_nae_lane_reset_txpll(uint64_t, int, int, int);
622 void xlp_nae_lane_reset_txpll(uint64_t, int, int, int);
623 void xlp_nae_config_lane_gmac(uint64_t, int);
624 void config_egress_fifo_carvings(uint64_t, int, int, int, int,
625 struct nae_port_config *);
626 void config_egress_fifo_credits(uint64_t, int, int, int, int,
627 struct nae_port_config *);
628 void nlm_config_freein_fifo_uniq_cfg(uint64_t, int, int);
629 void nlm_config_ucore_iface_mask_cfg(uint64_t, int, int);
630 int nlm_nae_init_netior(uint64_t nae_base, int nblocks);
631 void nlm_nae_init_ingress(uint64_t, uint32_t);
632 void nlm_nae_init_egress(uint64_t);
633 uint32_t ucore_spray_config(uint32_t, uint32_t, int);
634 void nlm_nae_init_ucore(uint64_t nae_base, int if_num, uint32_t ucore_mask);
635 int nlm_nae_open_if(uint64_t, int, int, int, uint32_t);
636 void nlm_mac_enable(uint64_t, int, int, int);
637 void nlm_mac_disable(uint64_t, int, int, int);
638 uint64_t nae_tx_desc(u_int, u_int, u_int, u_int, uint64_t);
639 void nlm_setup_l2type(uint64_t, int, uint32_t, uint32_t, uint32_t,
640 uint32_t, uint32_t, uint32_t);
641 void nlm_setup_l3ctable_mask(uint64_t, int, uint32_t, uint32_t);
642 void nlm_setup_l3ctable_even(uint64_t, int, uint32_t, uint32_t, uint32_t,
643 uint32_t, uint32_t);
644 void nlm_setup_l3ctable_odd(uint64_t, int, uint32_t, uint32_t, uint32_t,
645 uint32_t, uint32_t, uint32_t);
646 void nlm_setup_l4ctable_even(uint64_t, int, uint32_t, uint32_t, uint32_t,
647 uint32_t, uint32_t, uint32_t);
648 void nlm_setup_l4ctable_odd(uint64_t, int, uint32_t, uint32_t, uint32_t, uint32_t);
649 void nlm_enable_hardware_parser(uint64_t);
650 void nlm_enable_hardware_parser_per_port(uint64_t, int, int);
651 void nlm_prepad_enable(uint64_t, int);
652 void nlm_setup_1588_timer(uint64_t, struct nae_port_config *);
653
654 #endif /* !(LOCORE) && !(__ASSEMBLY__) */
655
656 #endif
657