1 /*- 2 * Copyright (c) 1998 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/sys/ia64/include/fpu.h 138674 2004-12-11 06:15:12Z marcel $ 27 */ 28 29 #ifndef _MACHINE_FPU_H_ 30 #define _MACHINE_FPU_H_ 31 32 /* 33 * Floating point status register bits. 34 */ 35 36 #define IA64_FPSR_TRAP_VD 0x0000000000000001L 37 #define IA64_FPSR_TRAP_DD 0x0000000000000002L 38 #define IA64_FPSR_TRAP_ZD 0x0000000000000004L 39 #define IA64_FPSR_TRAP_OD 0x0000000000000008L 40 #define IA64_FPSR_TRAP_UD 0x0000000000000010L 41 #define IA64_FPSR_TRAP_ID 0x0000000000000020L 42 #define IA64_FPSR_SF(i,v) ((v) << ((i)*13+6)) 43 44 #define IA64_SF_FTZ 0x0001L 45 #define IA64_SF_WRE 0x0002L 46 #define IA64_SF_PC 0x000cL 47 #define IA64_SF_PC_0 0x0000L 48 #define IA64_SF_PC_1 0x0004L 49 #define IA64_SF_PC_2 0x0008L 50 #define IA64_SF_PC_3 0x000cL 51 #define IA64_SF_RC 0x0030L 52 #define IA64_SF_RC_NEAREST 0x0000L 53 #define IA64_SF_RC_NEGINF 0x0010L 54 #define IA64_SF_RC_POSINF 0x0020L 55 #define IA64_SF_RC_TRUNC 0x0030L 56 #define IA64_SF_TD 0x0040L 57 #define IA64_SF_V 0x0080L 58 #define IA64_SF_D 0x0100L 59 #define IA64_SF_Z 0x0200L 60 #define IA64_SF_O 0x0400L 61 #define IA64_SF_U 0x0800L 62 #define IA64_SF_I 0x1000L 63 64 #define IA64_SF_DEFAULT (IA64_SF_PC_3 | IA64_SF_RC_NEAREST) 65 66 #define IA64_FPSR_DEFAULT (IA64_FPSR_TRAP_VD \ 67 | IA64_FPSR_TRAP_DD \ 68 | IA64_FPSR_TRAP_ZD \ 69 | IA64_FPSR_TRAP_OD \ 70 | IA64_FPSR_TRAP_UD \ 71 | IA64_FPSR_TRAP_ID \ 72 | IA64_FPSR_SF(0, IA64_SF_DEFAULT) \ 73 | IA64_FPSR_SF(1, (IA64_SF_DEFAULT \ 74 | IA64_SF_TD \ 75 | IA64_SF_WRE)) \ 76 | IA64_FPSR_SF(2, (IA64_SF_DEFAULT \ 77 | IA64_SF_TD)) \ 78 | IA64_FPSR_SF(3, (IA64_SF_DEFAULT \ 79 | IA64_SF_TD))) 80 81 struct fpswa_ret { 82 unsigned long status; 83 unsigned long err1; 84 unsigned long err2; 85 unsigned long err3; 86 }; 87 88 struct fpswa_bundle { 89 long double bits; /* Force 16-byte alignment. */ 90 }; 91 92 struct fpswa_fpctx { 93 unsigned long mask_low; /* f63 - f2 */ 94 unsigned long mask_high; /* f127 - f64 */ 95 union _ia64_fpreg *fp_low_preserved; /* f2 - f5 */ 96 union _ia64_fpreg *fp_low_volatile; /* f6 - f15 */ 97 union _ia64_fpreg *fp_high_preserved; /* f16 - f31 */ 98 union _ia64_fpreg *fp_high_volatile; /* f32 - f127 */ 99 }; 100 101 struct fpswa_iface { 102 unsigned int if_rev; 103 unsigned int __res; 104 struct fpswa_ret (*if_fpswa)(unsigned long, struct fpswa_bundle *, 105 unsigned long *, unsigned long *, unsigned long *, unsigned long *, 106 unsigned long *, struct fpswa_fpctx *); 107 }; 108 109 #endif /* ! _MACHINE_FPU_H_ */ 110