| /freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 699 EXTLOAD, enumerator
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| D | SelectionDAGNodes.h | 1903 cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
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| /freebsd-10-stable/contrib/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 123 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand); in AMDGPUTargetLowering()
126 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand); in AMDGPUTargetLowering()
129 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand); in AMDGPUTargetLowering()
132 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand); in AMDGPUTargetLowering()
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| D | AMDGPUInstructions.td | 121 L->getExtensionType() == ISD::EXTLOAD;
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| D | R600ISelLowering.cpp | 100 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom); in R600TargetLowering()
101 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom); in R600TargetLowering()
1274 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr, in LowerLOAD()
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| D | SIISelLowering.cpp | 128 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Expand); in SITargetLowering()
132 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); in SITargetLowering()
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| /freebsd-10-stable/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && in ExpandConstantFP()
290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, in ExpandConstantFP()
377 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, in ExpandUnalignedStore()
494 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in ExpandUnalignedLoad()
959 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
1091 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) { in LegalizeLoadOps()
1096 case ISD::EXTLOAD: in LegalizeLoadOps()
1116 assert(ExtType != ISD::EXTLOAD && in LegalizeLoadOps()
1120 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), in LegalizeLoadOps()
1403 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, in ExpandExtractFromVectorThroughStack()
[all …]
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| D | LegalizeVectorOps.cpp | 430 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR, in ExpandLoad()
480 case ISD::EXTLOAD: in ExpandLoad()
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| D | SelectionDAGDumper.cpp | 450 case ISD::EXTLOAD: OS << ", anyext"; break; in print_details()
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| D | DAGCombiner.cpp | 763 : ISD::EXTLOAD) in PromoteOperand()
985 : ISD::EXTLOAD) in PromoteLoad()
2629 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; in visitAND()
2638 if (Load->getExtensionType() == ISD::EXTLOAD) { in visitAND()
5071 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { in visitANY_EXTEND()
5078 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, in visitANY_EXTEND()
6736 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { in visitFP_EXTEND()
6738 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, in visitFP_EXTEND()
8931 TLI.isLoadExtLegal(ISD::EXTLOAD, StoreTy)) in MergeConsecutiveStores()
9464 ? ISD::ZEXTLOAD : ISD::EXTLOAD; in visitEXTRACT_VECTOR_ELT()
[all …]
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| D | LegalizeIntegerTypes.cpp | 417 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); in PromoteIntRes_LOAD()
1835 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); in ExpandIntRes_LOAD()
2854 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), in ExpandIntOp_UINT_TO_FP()
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| /freebsd-10-stable/contrib/llvm/lib/Target/SystemZ/ |
| D | SystemZOperators.td | 206 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD;
221 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD;
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| D | SystemZISelLowering.cpp | 196 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in SystemZTargetLowering()
251 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand); in SystemZTargetLowering()
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| /freebsd-10-stable/contrib/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 130 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in XCoreTargetLowering()
440 SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, in LowerLOAD()
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| /freebsd-10-stable/contrib/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 216 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in MipsTargetLowering()
221 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); in MipsTargetLowering()
374 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); in MipsTargetLowering()
1983 (ExtType == ISD::EXTLOAD)) in lowerLOAD()
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| D | MipsSEISelLowering.cpp | 56 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand); in MipsSETargetLowering()
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| /freebsd-10-stable/contrib/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 95 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in AArch64TargetLowering()
269 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); in AArch64TargetLowering()
270 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); in AArch64TargetLowering()
271 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand); in AArch64TargetLowering()
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| /freebsd-10-stable/contrib/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
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| /freebsd-10-stable/contrib/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1314 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); in HexagonTargetLowering()
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| /freebsd-10-stable/contrib/llvm/lib/Target/X86/ |
| D | X86InstrInfo.td | 769 if (ExtType == ISD::EXTLOAD)
777 if (ExtType == ISD::EXTLOAD)
787 if (ExtType == ISD::EXTLOAD)
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| D | X86ISelDAGToDAG.cpp | 544 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp, in PreprocessISelDAG()
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| /freebsd-10-stable/contrib/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); in SparcTargetLowering()
1383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); in SparcTargetLowering()
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| /freebsd-10-stable/contrib/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 619 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
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| /freebsd-10-stable/contrib/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 185 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); in NVPTXTargetLowering()
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| /freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 437 setLoadExtAction(ISD::EXTLOAD, VT, Expand); in PPCTargetLowering()
3921 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, in LowerCall_64SVR4()
4293 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, in LowerCall_Darwin()
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