| /freebsd-10-stable/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 733 EVT DstVT = TLI.getValueType(I->getType()); in SelectCast() local
736 DstVT == MVT::Other || !DstVT.isSimple()) in SelectCast()
741 if (!TLI.isTypeLegal(DstVT)) in SelectCast()
756 DstVT.getSimpleVT(), in SelectCast()
785 MVT DstVT = DstEVT.getSimpleVT(); in SelectBitCast() local
795 if (SrcVT == DstVT) { in SelectBitCast()
797 const TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); in SelectBitCast()
808 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); in SelectBitCast()
1069 EVT DstVT = TLI.getValueType(I->getType()); in SelectOperator() local
1070 if (DstVT.bitsGT(SrcVT)) in SelectOperator()
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| D | LegalizeIntegerTypes.cpp | 2693 EVT DstVT = N->getValueType(0); in ExpandIntOp_SINT_TO_FP() local
2694 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); in ExpandIntOp_SINT_TO_FP()
2697 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first; in ExpandIntOp_SINT_TO_FP()
2797 EVT DstVT = N->getValueType(0); in ExpandIntOp_UINT_TO_FP() local
2803 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT); in ExpandIntOp_UINT_TO_FP()
2807 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); in ExpandIntOp_UINT_TO_FP()
2854 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), in ExpandIntOp_UINT_TO_FP()
2859 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); in ExpandIntOp_UINT_TO_FP()
2863 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); in ExpandIntOp_UINT_TO_FP()
2866 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl).first; in ExpandIntOp_UINT_TO_FP()
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| /freebsd-10-stable/contrib/llvm/lib/Target/X86/ |
| D | X86SelectionDAGInfo.cpp | 252 EVT DstVT = Dst.getValueType(); in EmitTargetCodeForMemcpy() local
256 DAG.getNode(ISD::ADD, dl, DstVT, Dst, in EmitTargetCodeForMemcpy()
257 DAG.getConstant(Offset, DstVT)), in EmitTargetCodeForMemcpy()
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| D | X86FastISel.cpp | 88 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
338 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend() argument
341 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, in X86FastEmitExtend()
838 EVT DstVT = VA.getValVT(); in X86SelectRet() local
840 if (SrcVT != DstVT) { in X86SelectRet()
847 assert(DstVT == MVT::i32 && "X86 should always ext to i32"); in X86SelectRet()
857 SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, in X86SelectRet()
1069 EVT DstVT = TLI.getValueType(I->getType()); in X86SelectZExt() local
1070 if (!TLI.isTypeLegal(DstVT)) in X86SelectZExt()
1088 if (DstVT == MVT::i64) { in X86SelectZExt()
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| D | X86ISelDAGToDAG.cpp | 503 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
506 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
514 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
532 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. in PreprocessISelDAG()
534 MemVT = SrcIsSSE ? SrcVT : DstVT; in PreprocessISelDAG()
544 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp, in PreprocessISelDAG()
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| D | X86ISelLowering.cpp | 8716 EVT DstVT = Op.getValueType(); in LowerUINT_TO_FP() local
8717 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) in LowerUINT_TO_FP()
8721 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32) in LowerUINT_TO_FP()
8787 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); in LowerUINT_TO_FP()
13260 MVT DstVT = Op.getSimpleValueType(); in LowerBITCAST() local
13263 assert((DstVT == MVT::i64 || in LowerBITCAST()
13264 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && in LowerBITCAST()
13267 if (SrcVT==MVT::i64 && DstVT.isVector()) in LowerBITCAST()
13269 if (DstVT==MVT::i64 && SrcVT.isVector()) in LowerBITCAST()
13272 if (SrcVT.isVector() && DstVT.isVector()) in LowerBITCAST()
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| D | X86InstrSSE.td | 3727 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3736 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3743 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3751 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3757 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3767 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3774 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
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| D | X86InstrAVX512.td | 1590 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
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| /freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 914 MVT DstVT; in SelectIToFP() local
916 if (!isTypeLegal(DstTy, DstVT)) in SelectIToFP()
919 if (DstVT != MVT::f32 && DstVT != MVT::f64) in SelectIToFP()
947 if (DstVT == MVT::f32 && !PPCSubTarget.hasFPCVT()) in SelectIToFP()
969 if (DstVT == MVT::f32) in SelectIToFP()
1021 MVT DstVT, SrcVT; in SelectFPToI() local
1023 if (!isTypeLegal(DstTy, DstVT)) in SelectFPToI()
1026 if (DstVT != MVT::i32 && DstVT != MVT::i64) in SelectFPToI()
1030 if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget.hasFPCVT()) in SelectFPToI()
1062 if (DstVT == MVT::i32) in SelectFPToI()
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| /freebsd-10-stable/contrib/llvm/lib/Transforms/Scalar/ |
| D | CodeGenPrepare.cpp | 457 EVT DstVT = TLI.getValueType(CI->getType()); in OptimizeNoopCopyExpression() local
460 if (SrcVT.isInteger() != DstVT.isInteger()) in OptimizeNoopCopyExpression()
465 if (SrcVT.bitsLT(DstVT)) return false; in OptimizeNoopCopyExpression()
473 if (TLI.getTypeAction(CI->getContext(), DstVT) == in OptimizeNoopCopyExpression()
475 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); in OptimizeNoopCopyExpression()
478 if (SrcVT != DstVT) in OptimizeNoopCopyExpression()
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| /freebsd-10-stable/contrib/llvm/patches/ |
| D | patch-r267981-llvm-r211435-fix-ppc-fctiduz.diff | 31 if (DstVT != MVT::i32 && DstVT != MVT::i64)
35 + if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget.hasFPCVT())
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| /freebsd-10-stable/contrib/llvm/lib/Target/Mips/ |
| D | MipsMSAInstrInfo.td | 3516 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3518 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3573 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3576 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3581 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3584 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3589 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3591 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3593 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3595 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
[all …]
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| D | MipsDSPInstrInfo.td | 1278 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1280 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
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| /freebsd-10-stable/contrib/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1639 MVT DstVT; in SelectIToFP() local
1641 if (!isTypeLegal(Ty, DstVT)) in SelectIToFP()
1672 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
1684 MVT DstVT; in SelectFPToI() local
1686 if (!isTypeLegal(RetTy, DstVT)) in SelectFPToI()
1706 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
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| D | ARMISelLowering.cpp | 3848 EVT DstVT = N->getValueType(0); in ExpandBITCAST() local
3849 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && in ExpandBITCAST()
3853 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { in ExpandBITCAST()
3858 return DAG.getNode(ISD::BITCAST, dl, DstVT, in ExpandBITCAST()
3863 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { in ExpandBITCAST()
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