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Searched refs:DMA1_REGISTER_OFFSET (Results 1 – 4 of 4) sorted by relevance

/freebsd-10-stable/sys/dev/drm2/radeon/
Dni.c674 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()
1270 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
1272 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
1307 reg_offset = DMA1_REGISTER_OFFSET; in cayman_dma_resume()
1467 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_gpu_soft_reset_dma()
1469 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset_dma()
1547 dma_status_reg = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); in cayman_dma_is_lockup()
1675 DMA_RB_RPTR + DMA1_REGISTER_OFFSET, in cayman_startup()
1676 DMA_RB_WPTR + DMA1_REGISTER_OFFSET, in cayman_startup()
Dsi.c1717 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
2253 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset_dma()
2255 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset_dma()
3313 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
3314 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
3456 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
3540 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); in si_irq_set()
4231 DMA_RB_RPTR + DMA1_REGISTER_OFFSET, in si_startup()
4232 DMA_RB_WPTR + DMA1_REGISTER_OFFSET, in si_startup()
Dnid.h629 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ macro
Dsid.h1010 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ macro