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Searched refs:CondCode (Results 1 – 25 of 53) sorted by relevance

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/freebsd-10-stable/contrib/llvm/include/llvm/CodeGen/
DISDOpcodes.h719 enum CondCode { enum
752 inline bool isSignedIntSetCC(CondCode Code) { in isSignedIntSetCC()
758 inline bool isUnsignedIntSetCC(CondCode Code) { in isUnsignedIntSetCC()
765 inline bool isTrueWhenEqual(CondCode Cond) { in isTrueWhenEqual()
773 inline unsigned getUnorderedFlavor(CondCode Cond) { in getUnorderedFlavor()
779 CondCode getSetCCInverse(CondCode Operation, bool isInteger);
783 CondCode getSetCCSwappedOperands(CondCode Operation);
789 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
795 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
DAnalysis.h73 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
77 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
82 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
DSelectionDAG.h530 SDValue getCondCode(ISD::CondCode Cond);
658 ISD::CondCode Cond) {
684 SDValue True, SDValue False, ISD::CondCode Cond) {
1071 SDValue N2, ISD::CondCode Cond, SDLoc dl);
/freebsd-10-stable/contrib/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp32 enum CondCode { enum
134 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) in GetCondFromBranchOpc()
147 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) in GetCondBranchFromCond()
158 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) in GetOppositeBranchCondition()
218 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); in AnalyzeBranch()
240 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); in AnalyzeBranch()
294 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
303 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
399 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); in ReverseBranchCondition()
/freebsd-10-stable/contrib/llvm/lib/Target/X86/
DX86InstrInfo.h32 enum CondCode { enum
62 unsigned GetCondBranchFromCond(CondCode CC);
65 CondCode getCondFromCMovOpc(unsigned Opc);
69 CondCode GetOppositeBranchCondition(X86::CondCode CC);
DX86InstrInfo.cpp2455 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) { in getCondFromBranchOpc()
2478 static X86::CondCode getCondFromSETOpc(unsigned Opc) { in getCondFromSETOpc()
2501 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) { in getCondFromCMovOpc()
2555 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { in GetCondBranchFromCond()
2579 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { in GetOppositeBranchCondition()
2604 static X86::CondCode getSwappedCondition(X86::CondCode CC) { in getSwappedCondition()
2622 static unsigned getSETFromCond(X86::CondCode CC, in getSETFromCond()
2649 static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes, in getCMovFromCond()
2762 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode()); in AnalyzeBranch()
2824 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); in AnalyzeBranch()
[all …]
/freebsd-10-stable/contrib/llvm/include/llvm/Target/
DTargetSelectionDAG.td498 class CondCode; // ISD::CondCode enums
499 def SETOEQ : CondCode; def SETOGT : CondCode;
500 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
501 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
502 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
503 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
505 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
506 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
DTargetLowering.h533 getCondCodeAction(ISD::CondCode CC, MVT VT) const { in getCondCodeAction()
546 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { in isCondCodeLegal()
1034 void setCondCodeAction(ISD::CondCode CC, MVT VT, in setCondCodeAction()
1292 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { in setCmpLibcallCC()
1298 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { in getCmpLibcallCC()
1625 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1755 ISD::CondCode &CCCode, SDLoc DL) const;
1859 ISD::CondCode Cond, bool foldBooleans,
/freebsd-10-stable/contrib/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.h33 enum CondCode { enum
73 const char *MipsFCCToString(Mips::CondCode CC);
DMipsInstPrinter.cpp35 const char* Mips::MipsFCCToString(Mips::CondCode CC) { in MipsFCCToString()
220 O << MipsFCCToString((Mips::CondCode)MO.getImm()); in printFCCOperand()
/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp723 unsigned CondCode = MI->getOperand(3).getImm(); in EmitF128CSEL() local
749 .addImm(CondCode) in EmitF128CSEL()
1779 static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) { in IntCCToA64CC()
1807 ISD::CondCode CC, SDValue &A64cc, in getSelectableIntSetCC()
1862 A64CC::CondCodes CondCode = IntCCToA64CC(CC); in getSelectableIntSetCC() local
1863 A64cc = DAG.getConstant(CondCode, MVT::i32); in getSelectableIntSetCC()
1868 static A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC, in FPCCToA64CC()
1870 A64CC::CondCodes CondCode = A64CC::Invalid; in FPCCToA64CC() local
1876 case ISD::SETOEQ: CondCode = A64CC::EQ; break; in FPCCToA64CC()
1878 case ISD::SETOGT: CondCode = A64CC::GT; break; in FPCCToA64CC()
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DAArch64ISelLowering.h274 SDValue getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
/freebsd-10-stable/contrib/llvm/lib/CodeGen/
DAnalysis.cpp150 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { in getFCmpCondCode()
172 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) { in getFCmpCodeWithoutNaN()
187 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) { in getICmpCondCode()
/freebsd-10-stable/contrib/llvm/patches/
Dpatch-r262261-llvm-r199975-sparc.diff234 + unsigned CondCode) const {
295 + if (CondCode) {
300 + .addReg(ValReg).addReg(Rs2Reg).addImm(CondCode);
341 + unsigned CondCode = 0) const;
Dpatch-r262264-llvm-r200453-sparc.diff66 .addReg(ValReg).addReg(Rs2Reg).addImm(CondCode);
/freebsd-10-stable/contrib/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp113 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
472 ISD::CondCode CC, SDLoc dl) { in SelectCC()
569 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { in getPredicateForSetCC()
600 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { in getCRIdxForSetCC()
632 static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC) { in getVCmpInst()
714 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); in SelectSETCC()
1183 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); in Select()
1246 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); in Select()
1247 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); in Select() local
1248 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, in Select()
/freebsd-10-stable/contrib/llvm/lib/Target/ARM/
DARMISelLowering.cpp1218 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { in IntCCToARMCC()
1235 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in FPCCToARMCC() argument
1241 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; in FPCCToARMCC()
1243 case ISD::SETOGT: CondCode = ARMCC::GT; break; in FPCCToARMCC()
1245 case ISD::SETOGE: CondCode = ARMCC::GE; break; in FPCCToARMCC()
1246 case ISD::SETOLT: CondCode = ARMCC::MI; break; in FPCCToARMCC()
1247 case ISD::SETOLE: CondCode = ARMCC::LS; break; in FPCCToARMCC()
1248 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; in FPCCToARMCC()
1249 case ISD::SETO: CondCode = ARMCC::VC; break; in FPCCToARMCC()
1250 case ISD::SETUO: CondCode = ARMCC::VS; break; in FPCCToARMCC()
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/freebsd-10-stable/contrib/llvm/lib/Target/R600/
DR600ISelLowering.cpp877 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
878 ISD::CondCode InverseCC = in LowerSELECT_CC()
885 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC); in LowerSELECT_CC()
912 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
914 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode); in LowerSELECT_CC()
920 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger()); in LowerSELECT_CC()
932 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
1631 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get(); in PerformDAGCombine()
1643 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get(); in PerformDAGCombine()
/freebsd-10-stable/contrib/llvm/lib/Target/Sparc/
DSparcISelLowering.h174 unsigned CondCode = 0) const;
/freebsd-10-stable/contrib/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp668 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); in SoftenFloatOp_BR_CC()
714 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); in SoftenFloatOp_SELECT_CC()
737 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); in SoftenFloatOp_SETCC()
1308 ISD::CondCode &CCCode, in FloatExpandSetCCOperands()
1338 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); in ExpandFloatOp_BR_CC()
1431 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); in ExpandFloatOp_SELECT_CC()
1449 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); in ExpandFloatOp_SETCC()
DSelectionDAGBuilder.h209 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
219 ISD::CondCode CC;
DSelectionDAG.cpp222 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { in getSetCCSwappedOperands()
227 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits in getSetCCSwappedOperands()
234 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { in getSetCCInverse()
244 return ISD::CondCode(Operation); in getSetCCInverse()
251 static int isSignedOp(ISD::CondCode Opcode) { in isSignedOp()
271 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCOrOperation()
288 return ISD::CondCode(Op); in getSetCCOrOperation()
295 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCAndOperation()
302 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); in getSetCCAndOperation()
1332 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode()
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DLegalizeTypes.h290 void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
364 ISD::CondCode &CCCode, SDLoc dl);
494 ISD::CondCode &CCCode, SDLoc dl);
/freebsd-10-stable/contrib/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp217 struct CondCodeOp CondCode; member
257 return CondCode.Code; in getCondCode()
843 Op->CondCode.Code = Code; in CreateCondCode()
1529 A64CC::CondCodes CondCode = A64StringToCondCode(Tok); in ParseCondCodeOperand() local
1531 if (CondCode == A64CC::Invalid) in ParseCondCodeOperand()
1538 Operands.push_back(AArch64Operand::CreateCondCode(CondCode, S, E)); in ParseCondCodeOperand()
2551 OS << "<CondCode: " << CondCode.Code << ">"; in print()
/freebsd-10-stable/contrib/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp816 ISD::CondCode CC, in EmitCMP()
900 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
932 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in LowerSETCC()
999 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()

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