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Searched refs:AR_PHY_TIMING2 (Results 1 – 5 of 5) sorted by relevance

/freebsd-10-stable/sys/dev/ath/ath_hal/ar5416/
Dar5416phy.h141 #define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */ macro
/freebsd-10-stable/sys/contrib/dev/ath/ath_hal/ar9300/
Dar9300_spectral.c183 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING2, AR_PHY_TIMING2_DC_OFFSET, 0); in ar9300_disable_dc_offset()
511 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING2, AR_PHY_TIMING2_DC_OFFSET, in ar9300_stop_spectral_scan()
Dar9300_misc.c1906 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & in ar9300_ppm_force()
1908 OS_REG_WRITE(ah, AR_PHY_TIMING2, in ar9300_ppm_force()
1919 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM; in ar9300_ppm_un_force()
1920 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4); in ar9300_ppm_un_force()
1963 OS_REG_READ(ah, AR_PHY_TIMING2) & in ar9300_ppm_get_force_state()
Dar9300_reset.c4567 OS_REG_READ(ah, AR_PHY_TIMING2) & in ar9300_reset()
4695 tmp_reg = OS_REG_READ(ah, AR_PHY_TIMING2) & in ar9300_reset()
4697 OS_REG_WRITE(ah, AR_PHY_TIMING2, tmp_reg | save_force_val); in ar9300_reset()
5051 ahp->ah_dc_offset = MS(OS_REG_READ(ah, AR_PHY_TIMING2), in ar9300_reset()
Dar9300phy.h44 #define AR_PHY_TIMING2 AR_CHAN_OFFSET(BB_timing_controls_2) macro