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Searched refs:AR_PHY_PLL_CTL_40 (Results 1 – 5 of 5) sorted by relevance

/freebsd-10-stable/sys/dev/ath/ath_hal/ar5211/
Dar5211phy.h46 #define AR_PHY_PLL_CTL_40 0x18 /* 40 MHz */ macro
Dar5211_reset.c610 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40); in ar5211ChipReset()
/freebsd-10-stable/sys/dev/ath/ath_hal/ar5212/
Dar5212phy.h141 #define AR_PHY_PLL_CTL_40 0xaa /* 40 MHz */ macro
Dar5212_reset.c907 phyPLL = AR_PHY_PLL_CTL_40; in ar5212ChipReset()
/freebsd-10-stable/sys/dev/ath/ath_hal/ar5312/
Dar5312_reset.c681 phyPLL = AR_PHY_PLL_CTL_40; in ar5312ChipReset()