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Searched refs:wm_with_clock_ranges (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
HDsmu_helper.c658 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) in smu_set_watermarks_for_clocks_ranges() argument
663 if (!table || !wm_with_clock_ranges) in smu_set_watermarks_for_clocks_ranges()
666 … if (wm_with_clock_ranges->num_wm_dmif_sets > 4 || wm_with_clock_ranges->num_wm_mcif_sets > 4) in smu_set_watermarks_for_clocks_ranges()
669 for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) { in smu_set_watermarks_for_clocks_ranges()
672 … (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz / in smu_set_watermarks_for_clocks_ranges()
676 … (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz / in smu_set_watermarks_for_clocks_ranges()
680 … (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz / in smu_set_watermarks_for_clocks_ranges()
684 … (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz / in smu_set_watermarks_for_clocks_ranges()
687 wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; in smu_set_watermarks_for_clocks_ranges()
690 for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) { in smu_set_watermarks_for_clocks_ranges()
[all …]
HDsmu_helper.h110 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
HDsmu10_hwmgr.c1120 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in smu10_set_watermarks_for_clocks_ranges() local
1124 smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges); in smu10_set_watermarks_for_clocks_ranges()
HDvega12_hwmgr.c1781 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in vega12_set_watermarks_for_clocks_ranges() local
1786 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); in vega12_set_watermarks_for_clocks_ranges()
HDvega10_hwmgr.c4230 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range; in vega10_set_watermarks_for_clocks_ranges() local
4235 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); in vega10_set_watermarks_for_clocks_ranges()
/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/
HDamdgpu_dm_pp_smu.c419 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges) in dm_pp_notify_wm_clock_changes() argument
508 struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges; in pp_rv_set_wm_ranges() local
509 …struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks = wm_with_clock_ranges.wm_dmif_clock… in pp_rv_set_wm_ranges()
510 …struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks = wm_with_clock_ranges.wm_mcif_clock… in pp_rv_set_wm_ranges()
513 wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets; in pp_rv_set_wm_ranges()
514 wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets; in pp_rv_set_wm_ranges()
516 for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) { in pp_rv_set_wm_ranges()
532 for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) { in pp_rv_set_wm_ranges()
548 pp_funcs->set_watermarks_for_clocks_ranges(pp_handle, &wm_with_clock_ranges); in pp_rv_set_wm_ranges()
/dragonfly/sys/dev/drm/amd/display/dc/
HDdm_services.h220 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);