Home
last modified time | relevance | path

Searched refs:wm_clk_ranges (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce120/
HDdce120_resource.c813 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; in bw_calcs_data_update_from_pplib()
814 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = in bw_calcs_data_update_from_pplib()
816 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = in bw_calcs_data_update_from_pplib()
818 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()
820 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()
823 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; in bw_calcs_data_update_from_pplib()
824 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = in bw_calcs_data_update_from_pplib()
827 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; in bw_calcs_data_update_from_pplib()
828 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()
830 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()
[all …]
/dragonfly/sys/dev/drm/amd/display/dc/dce112/
HDdce112_resource.c1038 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; in bw_calcs_data_update_from_pplib()
1039 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = in bw_calcs_data_update_from_pplib()
1041 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = in bw_calcs_data_update_from_pplib()
1043 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()
1045 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()
1048 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; in bw_calcs_data_update_from_pplib()
1049 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = in bw_calcs_data_update_from_pplib()
1052 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; in bw_calcs_data_update_from_pplib()
1053 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()
1055 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = in bw_calcs_data_update_from_pplib()
[all …]
/dragonfly/sys/dev/drm/amd/display/dc/
HDdm_services_types.h146 struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS]; member