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Searched refs:vupdate_width (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dml/
HDdml1_display_rq_dlg_calc.c1044 unsigned int vupdate_width; in dml1_rq_dlg_get_dlg_params() local
1226 vupdate_width = e2e_pipe_param.pipe.dest.vupdate_width; in dml1_rq_dlg_get_dlg_params()
1296 line_setup = (double) (vupdate_offset + vupdate_width + vready_offset) / (double) htotal; in dml1_rq_dlg_get_dlg_params()
1322 DTRACE("DLG: %s: vupdate_width = %d", __func__, vupdate_width); in dml1_rq_dlg_get_dlg_params()
HDdisplay_mode_structs.h299 unsigned int vupdate_width; member
/dragonfly/sys/dev/drm/amd/display/dc/inc/hw/
HDtiming_generator.h76 int vupdate_width; member
/dragonfly/sys/dev/drm/amd/display/dc/calcs/
HDdcn_calcs.c424 input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width; in pipe_ctx_to_e2e_pipe_params()
1092 …pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2… in dcn_validate_bandwidth()
1133 …hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_id… in dcn_validate_bandwidth()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
HDdcn10_hw_sequencer.c660 … pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width; in dcn10_enable_stream_timing()
2212 … pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width; in program_all_pipe_in_tree()
HDdcn10_optc.c77 VUPDATE_WIDTH, optc->dlg_otg_param.vupdate_width); in optc1_program_global_sync()
HDdcn10_hubp.c123 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width in hubp1_vready_workaround()