Home
last modified time | relevance | path

Searched refs:virt (Results 1 – 25 of 34) sorted by relevance

12

/dragonfly/sys/dev/drm/amd/amdgpu/
HDamdgpu_virt.c55 AMDGPU_GEM_DOMAIN_VRAM, &adev->virt.csa_obj, in amdgpu_allocate_static_csa()
56 (u64 *)&adev->virt.csa_vmid0_addr, &ptr); in amdgpu_allocate_static_csa()
65 amdgpu_bo_free_kernel(&adev->virt.csa_obj, in amdgpu_free_static_csa()
66 (u64 *)&adev->virt.csa_vmid0_addr, in amdgpu_free_static_csa()
88 csa_tv.bo = &adev->virt.csa_obj->tbo; in amdgpu_map_static_csa()
100 *bo_va = amdgpu_vm_bo_add(adev, vm, adev->virt.csa_obj); in amdgpu_map_static_csa()
187 return adev->wb.wb[adev->virt.reg_val_offs]; in amdgpu_virt_kiq_rreg()
256 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_request_full_gpu() local
259 if (virt->ops && virt->ops->req_full_gpu) { in amdgpu_virt_request_full_gpu()
260 r = virt->ops->req_full_gpu(adev, init); in amdgpu_virt_request_full_gpu()
[all …]
HDamdgpu_vf_error.c41 mutex_lock(&adev->virt.vf_errors.lock); in amdgpu_vf_error_put()
42 index = adev->virt.vf_errors.write_count % AMDGPU_VF_ERROR_ENTRY_SIZE; in amdgpu_vf_error_put()
43 adev->virt.vf_errors.code [index] = error_code; in amdgpu_vf_error_put()
44 adev->virt.vf_errors.flags [index] = error_flags; in amdgpu_vf_error_put()
45 adev->virt.vf_errors.data [index] = error_data; in amdgpu_vf_error_put()
46 adev->virt.vf_errors.write_count ++; in amdgpu_vf_error_put()
47 mutex_unlock(&adev->virt.vf_errors.lock); in amdgpu_vf_error_put()
58 (!adev->virt.ops) || (!adev->virt.ops->trans_msg)) { in amdgpu_vf_error_trans_all()
69 mutex_lock(&adev->virt.vf_errors.lock); in amdgpu_vf_error_trans_all()
71 …if (adev->virt.vf_errors.write_count - adev->virt.vf_errors.read_count > AMDGPU_VF_ERROR_ENTRY_SIZ… in amdgpu_vf_error_trans_all()
[all …]
HDmxgpu_ai.c178 adev->virt.fw_reserve.checksum_key = in xgpu_ai_send_access_requests()
237 struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work); in xgpu_ai_mailbox_flr_work() local
238 struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt); in xgpu_ai_mailbox_flr_work()
296 schedule_work(&adev->virt.flr_work); in xgpu_ai_mailbox_rcv_irq()
324 adev->virt.ack_irq.num_types = 1; in xgpu_ai_mailbox_set_irq_funcs()
325 adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs; in xgpu_ai_mailbox_set_irq_funcs()
326 adev->virt.rcv_irq.num_types = 1; in xgpu_ai_mailbox_set_irq_funcs()
327 adev->virt.rcv_irq.funcs = &xgpu_ai_mailbox_rcv_irq_funcs; in xgpu_ai_mailbox_set_irq_funcs()
334 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq); in xgpu_ai_mailbox_add_irq_id()
338 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_ai_mailbox_add_irq_id()
[all …]
HDamdgpu_virt.h217 ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field = (val); \
222 (*val) = ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field; \
227 if (!adev->virt.fw_reserve.p_pf2vf) \
230 if (adev->virt.fw_reserve.p_pf2vf->version == 1) \
231 … *(val) = ((struct amdgim_pf2vf_info_v1 *)adev->virt.fw_reserve.p_pf2vf)->field; \
232 if (adev->virt.fw_reserve.p_pf2vf->version == 2) \
233 … *(val) = ((struct amdgim_pf2vf_info_v2 *)adev->virt.fw_reserve.p_pf2vf)->field; \
257 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
260 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
263 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
[all …]
HDmxgpu_vi.c514 struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work); in xgpu_vi_mailbox_flr_work() local
515 struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt); in xgpu_vi_mailbox_flr_work()
554 schedule_work(&adev->virt.flr_work); in xgpu_vi_mailbox_rcv_irq()
572 adev->virt.ack_irq.num_types = 1; in xgpu_vi_mailbox_set_irq_funcs()
573 adev->virt.ack_irq.funcs = &xgpu_vi_mailbox_ack_irq_funcs; in xgpu_vi_mailbox_set_irq_funcs()
574 adev->virt.rcv_irq.num_types = 1; in xgpu_vi_mailbox_set_irq_funcs()
575 adev->virt.rcv_irq.funcs = &xgpu_vi_mailbox_rcv_irq_funcs; in xgpu_vi_mailbox_set_irq_funcs()
582 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq); in xgpu_vi_mailbox_add_irq_id()
586 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 138, &adev->virt.ack_irq); in xgpu_vi_mailbox_add_irq_id()
588 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_vi_mailbox_add_irq_id()
[all …]
HDnbio_v6_1.c252 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; in nbio_v6_1_detect_hw_virt()
255 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; in nbio_v6_1_detect_hw_virt()
259 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; in nbio_v6_1_detect_hw_virt()
HDamdgpu_gfx.c210 r = amdgpu_device_wb_get(adev, &adev->virt.reg_val_offs); in amdgpu_gfx_kiq_init_ring()
236 amdgpu_device_wb_free(ring->adev, ring->adev->virt.reg_val_offs); in amdgpu_gfx_kiq_free_ring()
HDvi.c459 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; in vi_detect_hw_virtualization()
462 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; in vi_detect_hw_virtualization()
467 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; in vi_detect_hw_virtualization()
1593 adev->virt.ops = &xgpu_vi_virt_ops; in vi_set_ip_blocks()
HDamdgpu_device.c2243 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; in amdgpu_device_detect_sriov_bios()
2246 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; in amdgpu_device_detect_sriov_bios()
2249 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) in amdgpu_device_detect_sriov_bios()
2389 lockinit(&adev->virt.vf_errors.lock, "agvfel", 0, LK_CANRECURSE); in amdgpu_device_init()
2569 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_device_init()
2570 adev->virt.ops = NULL; in amdgpu_device_init()
3341 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { in amdgpu_device_reset_sriov()
HDnbio_v7_0.c276 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; in nbio_v7_0_detect_hw_virt()
HDvce_v4_0.c213 uint32_t *init_table = adev->virt.mm_table.cpu_addr; in vce_v4_0_sriov_start()
320 return vce_v4_0_mmsch_start(adev, &adev->virt.mm_table); in vce_v4_0_sriov_start()
HDamdgpu_kms.c950 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); in amdgpu_driver_postclose_kms()
953 amdgpu_bo_unreserve(adev->virt.csa_obj); in amdgpu_driver_postclose_kms()
HDuvd_v7_0.c779 uint32_t *init_table = adev->virt.mm_table.cpu_addr; in uvd_v7_0_sriov_start()
922 return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table); in uvd_v7_0_sriov_start()
HDsoc15.c519 adev->virt.ops = &xgpu_ai_virt_ops; in soc15_set_ip_blocks()
/dragonfly/sys/dev/virtual/amazon/ena/ena-com/
HDena_plat.h298 #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) (virt = NULL) argument
300 #define ENA_MEM_ALLOC_COHERENT_NODE(dmadev, size, virt, phys, handle, node, \ argument
303 ((virt) = NULL); \
307 #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, dma) \ argument
310 (virt) = (void *)(dma).vaddr; \
314 #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, dma) \ argument
318 bus_dmamem_free((dma).tag, (virt), (dma).map); \
321 (virt) = NULL; \
/dragonfly/contrib/gcc-8.0/gcc/cp/
HDdump.c171 tree virt = THUNK_VIRTUAL_OFFSET (t); in cp_dump_tree() local
179 if (virt) in cp_dump_tree()
180 virt = BINFO_VPTR_FIELD (virt); in cp_dump_tree()
183 if (virt) in cp_dump_tree()
184 dump_int (di, "virt", tree_to_shwi (virt)); in cp_dump_tree()
/dragonfly/contrib/gcc-4.7/gcc/cp/
HDdump.c328 tree virt = THUNK_VIRTUAL_OFFSET (t); in cp_dump_tree() local
336 if (virt) in cp_dump_tree()
337 virt = BINFO_VPTR_FIELD (virt); in cp_dump_tree()
340 if (virt) in cp_dump_tree()
341 dump_int (di, "virt", tree_low_cst (virt, 0)); in cp_dump_tree()
HDtree.c1480 copy_binfo (tree binfo, tree type, tree t, tree *igo_prev, int virt) in copy_binfo() argument
1484 if (virt) in copy_binfo()
1528 if (virt) in copy_binfo()
/dragonfly/contrib/ee/
HDnew_curse.c3276 struct _line *virt; in doupdate() local
3338 for (from_top = 0, curr = top_of_win, virt = window->first_line; in doupdate()
3342 if ((similar = Comp_line(curr, virt)) > 0) in doupdate()
3348 virt = virt->next_screen; in doupdate()
3352 virt = window->first_line; in doupdate()
3394 … if ((Comp_line(old, virt) == -1) && (!virtual_lines[from_top])) in doupdate()
3402 new1 = virt, count1 = 0; in doupdate()
3437 … for (offset = from_top, old=curr, new=virt; in doupdate()
3459 if (Comp_line(old, virt) == -1) in doupdate()
3467 new1 = virt, count1 = 0; in doupdate()
[all …]
/dragonfly/sys/dev/raid/mfi/
HDmfi_syspd.c292 void *virt = ap->a_virtual; in mfi_syspd_dump() local
303 sc->pd_id, offset / MFI_SECTOR_LEN, virt, len)) != 0) in mfi_syspd_dump()
HDmfi_disk.c327 void *virt = ap->a_virtual; in mfi_disk_dump() local
338 MFI_SECTOR_LEN, virt, len)) != 0) in mfi_disk_dump()
HDmfi.c2396 mfi_dump_blocks(struct mfi_softc *sc, int id, uint64_t lba, void *virt, in mfi_dump_blocks() argument
2424 cm->cm_data = virt; in mfi_dump_blocks()
2440 mfi_dump_syspd_blocks(struct mfi_softc *sc, int id, uint64_t lba, void *virt, in mfi_dump_syspd_blocks() argument
2471 cm->cm_data = virt; in mfi_dump_syspd_blocks()
/dragonfly/sys/dev/drm/include/uapi/drm/
HDdrm.h381 void __user *virt; member
/dragonfly/contrib/binutils-2.27/gas/doc/
HDc-mips.texi226 @itemx -mno-virt
229 @samp{-mno-virt} turns off this option.
1052 @kindex @code{.set virt}
1054 The directive @code{.set virt} makes the assembler accept instructions
/dragonfly/sys/platform/vkernel64/platform/
HDpmap.c2671 vm_offset_t virt = PHYS_TO_DMAP(phys); in pmap_zero_page_area() local
2673 bzero((char *)virt + off, size); in pmap_zero_page_area()

12