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/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
HDdcn10_optc.c121 asic_blank_end = (patched_crtc_timing.v_total - in get_start_vline()
157 start_line = dc_crtc_timing->v_total - (req_delta_lines - vsync_line) - 1; in optc1_program_vline_interrupt()
163 if (endLine >= dc_crtc_timing->v_total) in optc1_program_vline_interrupt()
185 uint32_t v_total; in optc1_program_timing() local
245 v_total = 2 * patched_crtc_timing.v_total; in optc1_program_timing()
248 v_total = patched_crtc_timing.v_total - 1; in optc1_program_timing()
251 OTG_V_TOTAL, v_total); in optc1_program_timing()
257 OTG_V_TOTAL_MAX, v_total); in optc1_program_timing()
259 OTG_V_TOTAL_MIN, v_total); in optc1_program_timing()
272 asic_blank_end = (patched_crtc_timing.v_total - in optc1_program_timing()
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HDdcn10_opp.c307 uint32_t space1_size = timing->v_total - timing->v_addressable; in opp1_program_stereo()
309 uint32_t space2_size = timing->v_total - timing->v_addressable; in opp1_program_stereo()
HDdcn10_stream_encoder.c418 DP_MSA_VTOTAL, crtc_timing->v_total); in enc1_stream_encoder_dp_set_stream_attribute()
434 v_active_start = crtc_timing->v_total - crtc_timing->v_border_top - in enc1_stream_encoder_dp_set_stream_attribute()
HDdcn10_optc.h449 uint32_t v_total; member
/dragonfly/sys/dev/drm/amd/display/modules/freesync/
HDfreesync.c280 temp = div_u64(temp, stream->timing.v_total); in mod_freesync_add_stream()
427 uint32_t vtotal = stream->timing.v_total; in calc_freesync_range()
504 unsigned int index, int *v_total) in calc_v_total_for_static_ramp() argument
574 ramp_current_frame_duration_in_ns, v_total); in calc_v_total_for_static_ramp()
660 streams[stream_idx]->timing.v_total) { in set_freesync_on_streams()
680 timing.v_total; in set_freesync_on_streams()
702 timing.v_total; in set_freesync_on_streams()
771 unsigned int index, v_total, inserted_frame_v_total = 0; in mod_freesync_handle_v_update() local
858 index, &v_total); in mod_freesync_handle_v_update()
866 v_total, in mod_freesync_handle_v_update()
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/dragonfly/sys/dev/drm/radeon/
HDradeon_legacy_tv.c429 unsigned int h_total, v_total, f_total; in radeon_legacy_tv_init_restarts() local
447 v_total = const_ptr->ver_total; in radeon_legacy_tv_init_restarts()
493 … v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); in radeon_legacy_tv_init_restarts()
495 … v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); in radeon_legacy_tv_init_restarts()
504 tv_dac->tv.vrestart = restart % v_total; in radeon_legacy_tv_init_restarts()
505 restart /= v_total; in radeon_legacy_tv_init_restarts()
/dragonfly/sys/dev/drm/amd/display/dc/dce/
HDdce_mem_input.c526 uint32_t v_total, in get_dmif_switch_time_us() argument
538 if (!h_total || v_total || !pix_clk_khz) in get_dmif_switch_time_us()
543 pixels_per_frame = h_total * v_total; in get_dmif_switch_time_us()
573 uint32_t v_total, in dce_mi_allocate_dmif() argument
581 v_total, in dce_mi_allocate_dmif()
HDdce_stream_encoder.c457 DP_MSA_VTOTAL, crtc_timing->v_total); in dce110_stream_encoder_dp_set_stream_attribute()
474 v_active_start = crtc_timing->v_total - crtc_timing->v_border_top - in dce110_stream_encoder_dp_set_stream_attribute()
/dragonfly/sys/dev/drm/amd/display/dc/dce120/
HDdce120_timing_generator.c109 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
467 timing->v_total - 1); in dce120_timing_generator_program_blanking()
475 timing->v_total - 1); in dce120_timing_generator_program_blanking()
480 timing->v_total - 1); in dce120_timing_generator_program_blanking()
492 tmp1 = timing->v_total - (v_sync_start + timing->v_border_top); in dce120_timing_generator_program_blanking()
693 timing->v_total - timing->v_addressable - in dce120_timing_generator_enable_advanced_request()
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
HDdce110_timing_generator.c313 bp_params.v_total = patched_crtc_timing.v_total; in dce110_timing_generator_program_timing_generator()
627 timing->v_total - 1, in dce110_timing_generator_program_blanking()
639 timing->v_total - 1, in dce110_timing_generator_program_blanking()
648 timing->v_total - 1, in dce110_timing_generator_program_blanking()
679 tmp = timing->v_total - (v_sync_start + timing->v_border_top); in dce110_timing_generator_program_blanking()
1141 timing->v_total > tg110->max_v_total) in dce110_timing_generator_validate_timing()
HDdce110_timing_generator_v.c272 timing->v_total - 1, in dce110_timing_generator_v_program_blanking()
303 tmp = timing->v_total - (v_sync_start + timing->v_border_top); in dce110_timing_generator_v_program_blanking()
HDdce110_hw_sequencer.c1176 (stream->timing.h_total*stream->timing.v_total); in build_audio_output()
2469 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) in dce110_fill_display_configs()
2470 / stream->timing.v_total; in dce110_fill_display_configs()
2487 (stream->timing.v_total in dce110_get_min_vblank_time_us()
2759 pipe_ctx->stream->timing.v_total, in dce110_apply_ctx_for_surface()
HDdce110_mem_input_v.c978 uint32_t v_total,/* for current stream */ in dce110_allocate_mem_input_v() argument
/dragonfly/sys/dev/drm/amd/display/dc/inc/hw/
HDmem_input.h121 uint32_t v_total,/* for current target */
/dragonfly/sys/dev/drm/amd/display/include/
HDbios_parser_types.h170 uint32_t v_total; member
/dragonfly/sys/dev/drm/amd/display/dc/calcs/
HDdce_calcs.c243 data->v_total[0] = data->v_total[4]; in calculate_bandwidth()
245 data->v_total[1] = data->v_total[4]; in calculate_bandwidth()
248 data->v_total[2] = data->v_total[5]; in calculate_bandwidth()
250 data->v_total[3] = data->v_total[5]; in calculate_bandwidth()
381 data->v_total[maximum_number_of_surfaces - 2] = data->v_total[5]; in calculate_bandwidth()
382 data->v_total[maximum_number_of_surfaces - 1] = data->v_total[5]; in calculate_bandwidth()
1427 …peed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div… in calculate_bandwidth()
1431 …ange_margin[k] = bw_sub(bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div… in calculate_bandwidth()
1989 …peed_change_latency_supported, bw_add(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[i], bw_sub(bw_div… in calculate_bandwidth()
2794 … data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); in populate_initial_data()
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HDdcn_calcs.c414 input->dest.vtotal = pipe->stream->timing.v_total; in pipe_ctx_to_e2e_pipe_params()
843 v->vtotal[input_idx] = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
846 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total in dcn_validate_bandwidth()
1098 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
1103 asic_blank_end = (pipe->stream->timing.v_total - in dcn_validate_bandwidth()
1139 … hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
HDcalcs_logger.h421 … DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_total[%d]:%d", i, bw_fixed_to_int(data->v_total[i])); in print_bw_calcs_data()
/dragonfly/sys/dev/drm/amd/display/dc/dml/
HDdisplay_mode_structs.h376 unsigned int v_total; member
/dragonfly/sys/dev/drm/amd/display/dc/core/
HDdc_stream.c342 stream->timing.v_total, in dc_stream_log()
HDdc_debug.c342 pipe_ctx->stream->timing.v_total, in context_timing_trace()
HDdc_resource.c334 if (stream1->timing.v_total != stream2->timing.v_total) in resource_are_streams_timing_synchronizable()
2287 hdmi_info.bits.bar_bottom = (stream->timing.v_total in set_avi_info_frame()
2338 && stream->timing.v_total >= 2160) in set_vendor_info_packet()
/dragonfly/sys/dev/drm/amd/display/dc/
HDdc_hw_types.h730 uint32_t v_total; member
/dragonfly/sys/dev/drm/amd/display/dc/inc/
HDdce_calcs.h389 struct bw_fixed v_total[maximum_number_of_surfaces]; member
/dragonfly/sys/dev/drm/amd/display/dc/bios/
HDcommand_table2.c391 cpu_to_le16((uint16_t)(bp_params->v_total - in set_crtc_using_dtd_timing_v3()

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