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Searched refs:u_int32_t (Results 1 – 25 of 1011) sorted by relevance

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/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/
HDosprey_reg_map.h87 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
89 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
90 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
91 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
92 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
93 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
94 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
95 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
96 volatile u_int32_t MAC_DMA_TXCFG; /* 0x30 - 0x34 */
97 volatile u_int32_t MAC_DMA_RXCFG; /* 0x34 - 0x38 */
[all …]
HDscorpion_reg_map.h78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
87 volatile u_int32_t MAC_DMA_TXCFG; /* 0x30 - 0x34 */
88 volatile u_int32_t MAC_DMA_RXCFG; /* 0x34 - 0x38 */
[all …]
HDscorpion_reg_map_macro.h83 #define MAC_DMA_CR__RXE_LP__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
86 ~0x00000004U) | ((u_int32_t)(1) << 2)
89 ~0x00000004U) | ((u_int32_t)(0) << 2)
95 #define MAC_DMA_CR__RXE_HP__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
98 ~0x00000008U) | ((u_int32_t)(1) << 3)
101 ~0x00000008U) | ((u_int32_t)(0) << 3)
107 #define MAC_DMA_CR__RXD__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
108 #define MAC_DMA_CR__RXD__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U)
111 ~0x00000020U) | (((u_int32_t)(src) <<\
114 (!((((u_int32_t)(src)\
[all …]
HDposeidon_reg_map_macro.h91 (u_int32_t)(src)\
94 ((u_int32_t)(src)\
98 ~0x00000001U) | ((u_int32_t)(src) &\
101 (!(((u_int32_t)(src)\
105 ~0x00000001U) | (u_int32_t)(1)
108 ~0x00000001U) | (u_int32_t)(0)
115 (((u_int32_t)(src)\
118 (((u_int32_t)(src)\
122 ~0x00000002U) | (((u_int32_t)(src) <<\
125 (!((((u_int32_t)(src)\
[all …]
HDosprey_reg_map_macro.h91 #define MAC_DMA_CR__RXE_LP__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
94 ~0x00000004U) | ((u_int32_t)(1) << 2)
97 ~0x00000004U) | ((u_int32_t)(0) << 2)
103 #define MAC_DMA_CR__RXE_HP__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
106 ~0x00000008U) | ((u_int32_t)(1) << 3)
109 ~0x00000008U) | ((u_int32_t)(0) << 3)
115 #define MAC_DMA_CR__RXD__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
116 #define MAC_DMA_CR__RXD__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U)
119 ~0x00000020U) | (((u_int32_t)(src) <<\
122 (!((((u_int32_t)(src)\
[all …]
HDar9300.h116 u_int32_t numStepsInLadder;
117 u_int32_t defaultStepNum;
122 u_int32_t currStepNum;
123 u_int32_t currGain;
124 u_int32_t targetGain;
125 u_int32_t loTrig;
126 u_int32_t hiTrig;
127 u_int32_t gainFCorrection;
128 u_int32_t active;
177 u_int32_t listen_time;
[all …]
HDwasp_reg_map.h21 volatile u_int32_t HOST_INTF_RESET_CONTROL; /* 0x4000 - 0x4004 */
22 volatile u_int32_t HOST_INTF_PM_CTRL; /* 0x4004 - 0x4008 */
23 volatile u_int32_t HOST_INTF_TIMEOUT; /* 0x4008 - 0x400c */
24 volatile u_int32_t HOST_INTF_SREV; /* 0x400c - 0x4010 */
25 volatile u_int32_t HOST_INTF_INTR_SYNC_CAUSE; /* 0x4010 - 0x4014 */
26 volatile u_int32_t HOST_INTF_INTR_SYNC_ENABLE; /* 0x4014 - 0x4018 */
27 volatile u_int32_t HOST_INTF_INTR_ASYNC_MASK; /* 0x4018 - 0x401c */
28 volatile u_int32_t HOST_INTF_INTR_SYNC_MASK; /* 0x401c - 0x4020 */
29 volatile u_int32_t HOST_INTF_INTR_ASYNC_CAUSE; /* 0x4020 - 0x4024 */
30 volatile u_int32_t HOST_INTF_INTR_ASYNC_ENABLE; /* 0x4024 - 0x4028 */
[all …]
HDar9300desc.h30 u_int32_t ds_info;
31 u_int32_t status1;
32 u_int32_t status2;
33 u_int32_t status3;
34 u_int32_t status4;
35 u_int32_t status5;
36 u_int32_t status6;
37 u_int32_t status7;
38 u_int32_t status8;
42 u_int32_t ds_info;
[all …]
/dragonfly/sys/dev/netif/ath/ath/
HDif_athioctl.h39 u_int32_t aggr_pkts[64];
40 u_int32_t aggr_single_pkt;
41 u_int32_t aggr_nonbaw_pkt;
42 u_int32_t aggr_aggr_pkt;
43 u_int32_t aggr_baw_closed_single_pkt;
44 u_int32_t aggr_low_hwq_single_pkt;
45 u_int32_t aggr_sched_nopkt;
46 u_int32_t aggr_rts_aggr_limited;
50 u_int32_t sync_intr[32];
54 u_int32_t ast_watchdog; /* device reset by watchdog */
[all …]
/dragonfly/sys/dev/raid/arcmsr/
HDarcmsr.h180 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16)
181 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff)
198 u_int32_t HeaderLength;
200 u_int32_t Timeout;
201 u_int32_t ControlCode;
202 u_int32_t ReturnCode;
203 u_int32_t Length;
487 u_int32_t resrved0[4]; /*0000 000F*/
488 u_int32_t inbound_msgaddr0; /*0010 0013*/
489 u_int32_t inbound_msgaddr1; /*0014 0017*/
[all …]
/dragonfly/sys/dev/raid/hptiop/
HDhptiop.h60 u_int32_t resrved0[4];
61 u_int32_t inbound_msgaddr0;
62 u_int32_t inbound_msgaddr1;
63 u_int32_t outbound_msgaddr0;
64 u_int32_t outbound_msgaddr1;
65 u_int32_t inbound_doorbell;
66 u_int32_t inbound_intstatus;
67 u_int32_t inbound_intmask;
68 u_int32_t outbound_doorbell;
69 u_int32_t outbound_intstatus;
[all …]
/dragonfly/sys/dev/raid/aac/
HDaacreg.h85 u_int32_t aq_fib_size; /* FIB size in bytes */
86 u_int32_t aq_fib_addr; /* receiver-space address of the FIB */
98 u_int32_t qt_qindex[AAC_QUEUE_COUNT][2];
131 u_int32_t Flink;
132 u_int32_t Blink;
140 u_int32_t XferState;
146 u_int32_t SenderFibAddress;
147 u_int32_t ReceiverFibAddress;
148 u_int32_t SenderData;
151 u_int32_t ReceiverTimeStart;
[all …]
/dragonfly/sys/crypto/rijndael/
HDrijndael-api-fst.c112 ((u_int32_t*)block)[0] ^= ((u_int32_t*)iv)[0]; in rijndael_blockEncrypt()
113 ((u_int32_t*)block)[1] ^= ((u_int32_t*)iv)[1]; in rijndael_blockEncrypt()
114 ((u_int32_t*)block)[2] ^= ((u_int32_t*)iv)[2]; in rijndael_blockEncrypt()
115 ((u_int32_t*)block)[3] ^= ((u_int32_t*)iv)[3]; in rijndael_blockEncrypt()
117 ((u_int32_t*)block)[0] = ((u_int32_t*)cipher->IV)[0] ^ ((u_int32_t*)input)[0]; in rijndael_blockEncrypt()
118 ((u_int32_t*)block)[1] = ((u_int32_t*)cipher->IV)[1] ^ ((u_int32_t*)input)[1]; in rijndael_blockEncrypt()
119 ((u_int32_t*)block)[2] = ((u_int32_t*)cipher->IV)[2] ^ ((u_int32_t*)input)[2]; in rijndael_blockEncrypt()
120 ((u_int32_t*)block)[3] = ((u_int32_t*)cipher->IV)[3] ^ ((u_int32_t*)input)[3]; in rijndael_blockEncrypt()
128 ((u_int32_t*)block)[0] ^= ((u_int32_t*)iv)[0]; in rijndael_blockEncrypt()
129 ((u_int32_t*)block)[1] ^= ((u_int32_t*)iv)[1]; in rijndael_blockEncrypt()
[all …]
/dragonfly/sys/dev/raid/mrsas/
HDmrsas.h145 u_int32_t regLockLength; // 0x10 - 0x13
216 u_int32_t Length;
225 u_int32_t FlagsLength;
228 u_int32_t Address32;
237 u_int32_t PrimaryReferenceTag; /* 0x14 */
240 u_int32_t TransferLength; /* 0x1C */
251 u_int32_t Address32;
259 u_int32_t Address;
260 u_int32_t FlagsLength;
266 u_int32_t Length;
[all …]
/dragonfly/sys/dev/disk/nata/
HData-raid.h93 u_int32_t cylinders;
124 u_int32_t magic_0;
127 u_int32_t generation;
132 u_int32_t dummy_2;
133 u_int32_t dummy_3;
134 u_int32_t flags;
135 u_int32_t timestamp;
136 u_int32_t dummy_4[4];
137 u_int32_t dummy_5[4];
141 u_int32_t magic_0;
[all …]
/dragonfly/sys/dev/netif/txp/
HDif_txpreg.h233 volatile u_int32_t tx_addrlo; /* virt addr low word */
234 volatile u_int32_t tx_addrhi; /* virt addr high word */
235 volatile u_int32_t tx_pflags; /* processing flags */
265 volatile u_int32_t rx_vaddrlo; /* virtual address, lo word */
266 volatile u_int32_t rx_vaddrhi; /* virtual address, hi word */
272 volatile u_int32_t rx_stat; /* status */
275 volatile u_int32_t rx_vlan; /* vlan tag/priority */
321 volatile u_int32_t rb_paddrlo;
322 volatile u_int32_t rb_paddrhi;
324 volatile u_int32_t rb_vaddrlo;
[all …]
/dragonfly/sys/platform/pc64/apic/
HDapicreg.h360 u_int32_t id; PAD3; /* 0020 R/W */
361 u_int32_t version; PAD3; /* 0030 RO */
366 u_int32_t tpr; PAD3;
367 u_int32_t apr; PAD3;
368 u_int32_t ppr; PAD3;
369 u_int32_t eoi; PAD3;
371 u_int32_t ldr; PAD3;
372 u_int32_t dfr; PAD3;
373 u_int32_t svr; PAD3;
374 u_int32_t isr0; PAD3;
[all …]
/dragonfly/sys/dev/crypto/safe/
HDsafevar.h62 u_int32_t dma_paddr; /* physical address */
138 u_int32_t ses_used;
139 u_int32_t ses_klen; /* key length in bits */
140 u_int32_t ses_key[8]; /* DES/3DES/AES key */
141 u_int32_t ses_mlen; /* hmac length in bytes */
142 u_int32_t ses_hminner[5]; /* hmac inner state */
143 u_int32_t ses_hmouter[5]; /* hmac outer state */
144 u_int32_t ses_iv[4]; /* DES/3DES/AES iv */
191 u_int32_t st_ipackets;
192 u_int32_t st_opackets;
[all …]
/dragonfly/sys/vfs/nfs/
HDnfsproto.h231 #define nfstov_mode(a) (fxdr_unsigned(u_int32_t, (a)) & ALLPERMS)
234 #define nfsv2tov_type(a) nv2tov_type[fxdr_unsigned(u_int32_t,(a))&0x7]
235 #define nfsv3tov_type(a) nv3tov_type[fxdr_unsigned(u_int32_t,(a))&0x7]
259 u_int32_t nfsv2_sec;
260 u_int32_t nfsv2_usec;
265 u_int32_t nfsv3_sec;
266 u_int32_t nfsv3_nsec;
275 u_int32_t nfsuquad[2];
283 u_int32_t lval[2];
292 u_int32_t specdata1;
[all …]
/dragonfly/sys/dev/crypto/ubsec/
HDubsecvar.h60 u_int32_t dma_paddr;
120 u_int32_t d_macbuf[5];
189 u_int32_t sc_statmask; /* interrupt status mask */
215 u_int32_t ses_used;
216 u_int32_t ses_deskey[6]; /* 3DES key */
217 u_int32_t ses_mlen; /* hmac length */
218 u_int32_t ses_hminner[5]; /* hmac inner state */
219 u_int32_t ses_hmouter[5]; /* hmac outer state */
220 u_int32_t ses_iv[2]; /* [3]DES iv */
227 u_int32_t hst_ipackets;
[all …]
/dragonfly/sys/dev/netif/sf/
HDif_sfreg.h560 (SF_MIIADDR_BASE + (phy * SF_MII_BLOCKS * sizeof(u_int32_t)) + \
561 (reg * sizeof(u_int32_t)))
670 u_int32_t sf_valid:1,
673 u_int32_t sf_pad0;
675 u_int32_t sf_pad1;
684 u_int32_t sf_valid:1,
687 u_int32_t sf_addrhi;
689 u_int32_t sf_pad;
698 u_int32_t sf_len:16,
709 u_int32_t sf_len:16,
[all …]
/dragonfly/sys/dev/raid/ciss/
HDcissreg.h40 u_int32_t target:24; /* SCSI target */
41 u_int32_t bus:6; /* SCSI bus */
42 u_int32_t mode:2; /* CISS_HDR_ADDRESS_MODE_* */
43 u_int32_t extra_address; /* SCSI-3 level-2 and level-3 address bytes */
47 u_int32_t lun:30; /* logical device ID */
48 u_int32_t mode:2; /* CISS_HDR_ADDRESS_MODE_LOGICAL */
49 u_int32_t :32; /* reserved */
53 u_int32_t :30;
54 u_int32_t mode:2;
55 u_int32_t :32;
[all …]
/dragonfly/sys/dev/netif/re/
HDre.h618 u_int32_t ul[4];
621 u_int32_t Frame_Length:14;
622 u_int32_t TCPF:1;
623 u_int32_t UDPF:1;
624 u_int32_t IPF:1;
625 u_int32_t TCPT:1;
626 u_int32_t UDPT:1;
627 u_int32_t CRC:1;
628 u_int32_t RUNT:1;
629 u_int32_t RES:1;
[all …]
/dragonfly/sys/dev/raid/asr/
HDsys_info.h417 u_int32_t command_count[256]; /* We assume MAX 256 SCSI commands */
418 u_int32_t max_command_time[256];
419 u_int32_t min_command_time[256];
421 u_int32_t min_intr_time;
422 u_int32_t max_intr_time;
423 u_int32_t max_intr_gap;
424 u_int32_t max_ht_time;
425 u_int32_t aborted_interrupts;
426 u_int32_t spurious_interrupts;
427 u_int32_t aborted_requests;
[all …]
/dragonfly/sys/dev/raid/dpt/
HDdpt.h437 u_int32_t foo_length; /* Should return 0x22, 0x24, etc */
444 u_int32_t signature; /* Signature MUST be "EATA". ntohl()`ed */
466 u_int32_t cplen; /* CP length: number of valid cp bytes */
468 u_int32_t splen; /* Returned bytes for a received SP command */
502 u_int32_t length; /* True length, after ntohl conversion */
507 u_int32_t seg_addr; /* All fields in network byte order */
508 u_int32_t seg_len;
521 u_int32_t residue_len; /* Number of bytes not transferred */
523 u_int32_t ccb_busaddr;
576 u_int32_t extendedMemSize; /* in KB */
[all …]

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