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/dragonfly/sys/dev/netif/ig_hal/
HDe1000_nvm.h39 u16 word[2];
40 u16 *pba_block;
45 u16 eep_major;
46 u16 eep_minor;
47 u16 eep_build;
54 u16 or_major;
55 u16 or_build;
56 u16 or_patch;
61 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c);
63 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data);
[all …]
HDe1000_vf.h95 u16 pkt_info;
97 u16 hdr_info;
103 u16 ip_id; /* IP id */
104 u16 csum; /* Packet Checksum */
110 u16 length; /* Packet length */
111 u16 vlan; /* VLAN tag */
205 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
222 u16 mta_reg_count;
223 u16 rar_entry_count;
230 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
[all …]
HDe1000_hw.h406 #define __le16 u16
677 u16 vlan_id;
679 u16 reserved2;
702 u16 reserved1;
703 u16 reserved2;
704 u16 command_length;
731 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
748 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
749 void (*release_swfw_sync)(struct e1000_hw *, u16);
777 s32 (*set_page)(struct e1000_hw *, u16);
[all …]
HDe1000_phy.h39 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
42 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
43 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data);
70 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
73 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
74 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
75 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
76 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
77 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
78 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
[all …]
HDe1000_nvm.c70 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b, in e1000_null_read_nvm()
71 u16 E1000_UNUSEDARG *c) in e1000_null_read_nvm()
93 u16 E1000_UNUSEDARG *data) in e1000_null_led_default()
107 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b, in e1000_null_write_nvm()
108 u16 E1000_UNUSEDARG *c) in e1000_null_write_nvm()
154 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) in e1000_shift_out_eec_bits()
201 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) in e1000_shift_in_eec_bits()
205 u16 data; in e1000_shift_in_eec_bits()
404 u16 timeout = NVM_MAX_RETRY_SPI; in e1000_ready_nvm_eeprom()
447 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) in e1000_read_nvm_spi()
[all …]
HDe1000_mbx.c42 u16 E1000_UNUSEDARG mbx_id) in e1000_null_mbx_check_for_flag()
55 u16 E1000_UNUSEDARG size, in e1000_null_mbx_transact()
56 u16 E1000_UNUSEDARG mbx_id) in e1000_null_mbx_transact()
72 s32 e1000_read_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id) in e1000_read_mbx()
98 s32 e1000_write_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id) in e1000_write_mbx()
121 s32 e1000_check_for_msg(struct e1000_hw *hw, u16 mbx_id) in e1000_check_for_msg()
141 s32 e1000_check_for_ack(struct e1000_hw *hw, u16 mbx_id) in e1000_check_for_ack()
161 s32 e1000_check_for_rst(struct e1000_hw *hw, u16 mbx_id) in e1000_check_for_rst()
181 static s32 e1000_poll_for_msg(struct e1000_hw *hw, u16 mbx_id) in e1000_poll_for_msg()
212 static s32 e1000_poll_for_ack(struct e1000_hw *hw, u16 mbx_id) in e1000_poll_for_ack()
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HDe1000_i210.h42 s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset,
43 u16 words, u16 *data);
44 s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset,
45 u16 words, u16 *data);
48 s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
49 void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
50 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
51 u16 *data);
52 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
53 u16 data);
[all …]
HDe1000_mbx.h95 s32 e1000_read_mbx(struct e1000_hw *, u32 *, u16, u16);
96 s32 e1000_write_mbx(struct e1000_hw *, u32 *, u16, u16);
97 s32 e1000_read_posted_mbx(struct e1000_hw *, u32 *, u16, u16);
98 s32 e1000_write_posted_mbx(struct e1000_hw *, u32 *, u16, u16);
99 s32 e1000_check_for_msg(struct e1000_hw *, u16);
100 s32 e1000_check_for_ack(struct e1000_hw *, u16);
101 s32 e1000_check_for_rst(struct e1000_hw *, u16);
HDe1000_i210.c41 static s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
42 u16 *data);
44 static s32 e1000_valid_led_default_i210(struct e1000_hw *hw, u16 *data);
88 s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask) in e1000_acquire_swfw_sync_i210()
140 void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask) in e1000_release_swfw_sync_i210()
235 s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words, in e1000_read_nvm_srrd_i210()
236 u16 *data) in e1000_read_nvm_srrd_i210()
239 u16 i, count; in e1000_read_nvm_srrd_i210()
280 s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words, in e1000_write_nvm_srwr_i210()
281 u16 *data) in e1000_write_nvm_srwr_i210()
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/dragonfly/sys/dev/drm/i915/
HDintel_vbt_defs.h55 u16 version;
56 u16 header_size;
57 u16 vbt_size;
73 u16 version;
74 u16 header_size;
75 u16 bdb_size;
89 u16 code_segment;
336 u16 handle;
337 u16 device_type; /* See DEVICE_TYPE_* above */
347 u16 dtd_buf_ptr; /* 161 */
[all …]
HDintel_bios.h42 u16 t1_t3;
43 u16 t8;
44 u16 t9;
45 u16 t10;
46 u16 t11_t12;
87 u16 panel_id;
127 u16 dual_link:2;
128 u16 lane_cnt:2;
129 u16 pixel_overlap:3;
130 u16 rgb_flip:1;
[all …]
HDintel_dsi.h50 u16 ports;
59 u16 operation_mode;
81 u16 dcs_backlight_ports;
82 u16 dcs_cabc_ports;
89 u16 lp_byte_clk;
92 u16 lp_rx_timeout;
93 u16 turn_arnd_val;
94 u16 rst_timer_val;
95 u16 hs_to_lp_count;
96 u16 clk_lp_to_hs_count;
[all …]
/dragonfly/sys/dev/virtual/amazon/ena/ena-com/
HDena_com.h114 u16 len; /**< Buffer length in bytes */
118 u16 len;
119 u16 req_id;
130 u16 mss;
131 u16 l3_hdr_len;
132 u16 l3_hdr_offset;
133 u16 l4_hdr_len; /* In words */
138 u16 desc_stride_ctrl;
140 u16 desc_list_entry_size;
141 u16 descs_num_before_header;
[all …]
/dragonfly/sys/dev/netif/ix/
HDixgbe_common.h47 u16 word[2];
48 u16 *pba_block;
54 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
63 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
64 u32 eeprom_buf_size, u16 max_pba_block_size,
66 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
68 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
69 u32 eeprom_buf_size, u16 *pba_block_size);
72 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status);
81 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
[all …]
HDixgbe_api.h70 u16 *phy_data);
72 u16 phy_data);
100 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);
101 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
102 u16 words, u16 *data);
103 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
104 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
105 u16 words, u16 *data);
107 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
136 u8 ver, u16 len, char *driver_ver);
[all …]
HDixgbe_x540.h50 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data);
51 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, u16 offset, u16 words,
52 u16 *data);
53 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data);
54 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, u16 offset, u16 words,
55 u16 *data);
57 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val);
HDixgbe_mbx.h155 s32 ixgbe_read_mbx(struct ixgbe_hw *, u32 *, u16, u16);
156 s32 ixgbe_write_mbx(struct ixgbe_hw *, u32 *, u16, u16);
157 s32 ixgbe_read_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);
158 s32 ixgbe_write_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);
159 s32 ixgbe_check_for_msg(struct ixgbe_hw *, u16);
160 s32 ixgbe_check_for_ack(struct ixgbe_hw *, u16);
161 s32 ixgbe_check_for_rst(struct ixgbe_hw *, u16);
HDixgbe_x550.h48 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size);
49 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val);
52 u16 offset, u16 words, u16 *data);
53 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
54 u16 data);
56 u16 offset, u16 words, u16 *data);
57 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
58 u16 *data);
59 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
60 u16 data);
[all …]
HDixgbe_mbx.c47 s32 ixgbe_read_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id) in ixgbe_read_mbx()
73 s32 ixgbe_write_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id) in ixgbe_write_mbx()
97 s32 ixgbe_check_for_msg(struct ixgbe_hw *hw, u16 mbx_id) in ixgbe_check_for_msg()
117 s32 ixgbe_check_for_ack(struct ixgbe_hw *hw, u16 mbx_id) in ixgbe_check_for_ack()
137 s32 ixgbe_check_for_rst(struct ixgbe_hw *hw, u16 mbx_id) in ixgbe_check_for_rst()
157 static s32 ixgbe_poll_for_msg(struct ixgbe_hw *hw, u16 mbx_id) in ixgbe_poll_for_msg()
189 static s32 ixgbe_poll_for_ack(struct ixgbe_hw *hw, u16 mbx_id) in ixgbe_poll_for_ack()
224 s32 ixgbe_read_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id) in ixgbe_read_posted_mbx()
253 s32 ixgbe_write_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, in ixgbe_write_posted_mbx()
254 u16 mbx_id) in ixgbe_write_posted_mbx()
[all …]
/dragonfly/contrib/wpa_supplicant/src/common/
HDgas.h15 struct wpabuf * gas_build_initial_resp(u8 dialog_token, u16 status_code,
16 u16 comeback_delay, size_t size);
18 gas_build_comeback_resp(u8 dialog_token, u16 status_code, u8 frag_id, u8 more,
19 u16 comeback_delay, size_t size);
21 struct wpabuf * gas_anqp_build_initial_resp(u8 dialog_token, u16 status_code,
22 u16 comeback_delay, size_t size);
24 u16 status_code,
25 u16 comeback_delay,
27 struct wpabuf * gas_anqp_build_comeback_resp(u8 dialog_token, u16 status_code,
29 u16 comeback_delay, size_t size);
[all …]
/dragonfly/sys/dev/drm/amd/amdgpu/
HDamdgpu_dpm.h100 u16 vddc;
101 u16 vddci;
111 u16 v;
121 u16 vddc;
125 u16 vddc1;
126 u16 vddc2;
127 u16 vddc3;
137 u16 voltage;
150 u16 v;
161 u16 v;
[all …]
HDamdgpu_atombios.h108 u16 s1;
123 u16 value;
172 u16 *leakage_id);
175 u16 *vddc, u16 *vddci,
176 u16 virtual_voltage_id,
177 u16 vbios_voltage_id);
180 u16 virtual_voltage_id,
181 u16 *voltage);
204 u16 voltage_id, u16 *voltage);
206 u16 *voltage,
[all …]
/dragonfly/contrib/wpa_supplicant/src/wps/
HDwps_attr_parse.h73 u16 manufacturer_len;
74 u16 model_name_len;
75 u16 model_number_len;
76 u16 serial_number_len;
77 u16 dev_name_len;
78 u16 public_key_len;
79 u16 encr_settings_len;
80 u16 ssid_len;
81 u16 network_key_len;
82 u16 authorized_macs_len;
[all …]
HDwps.h50 u16 auth_type;
51 u16 encr_type;
98 u16 config_methods;
167 u16 dev_pw_id;
245 struct wpabuf * wps_build_probe_req_ie(u16 pw_id, struct wps_device_data *dev,
327 void (*set_sel_reg_cb)(void *ctx, int sel_reg, u16 dev_passwd_id,
328 u16 sel_reg_config_methods);
342 const u8 *pri_dev_type, u16 config_methods,
343 u16 dev_password_id, u8 request_type,
527 u16 config_methods;
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/dragonfly/sys/dev/drm/radeon/
HDci_dpm.h42 u16 pcie_lane;
46 u16 performance_level_count;
84 u16 valid_flag;
100 u16 count;
101 u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT];
102 u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT];
117 u16 mvdd_bootup_value;
118 u16 vddc_bootup_value;
119 u16 vddci_bootup_value;
122 u16 pcie_gen_bootup_value;
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