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Searched refs:sclk_table (Results 1 – 14 of 14) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
HDsmu7_hwmgr.c631 &data->dpm_table.sclk_table, in smu7_reset_dpm_tables()
689 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v0()
692 … if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
694 … data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v0()
696 …data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
697 data->dpm_table.sclk_table.count++; in smu7_setup_dpm_tables_v0()
783 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v1()
785 … if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != in smu7_setup_dpm_tables_v1()
788 … data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v1()
791 … data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = in smu7_setup_dpm_tables_v1()
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HDprocess_pptables_v1_0.c417 phm_ppt_v1_clock_voltage_dependency_table *sclk_table; in get_sclk_voltage_dependency_table() local
431 sclk_table = kzalloc(table_size, GFP_KERNEL); in get_sclk_voltage_dependency_table()
433 if (NULL == sclk_table) in get_sclk_voltage_dependency_table()
436 sclk_table->count = (uint32_t)tonga_table->ucNumEntries; in get_sclk_voltage_dependency_table()
444 entries, sclk_table, i); in get_sclk_voltage_dependency_table()
463 sclk_table = kzalloc(table_size, GFP_KERNEL); in get_sclk_voltage_dependency_table()
465 if (NULL == sclk_table) in get_sclk_voltage_dependency_table()
468 sclk_table->count = (uint32_t)polaris_table->ucNumEntries; in get_sclk_voltage_dependency_table()
476 entries, sclk_table, i); in get_sclk_voltage_dependency_table()
486 *pp_tonga_sclk_dep_table = sclk_table; in get_sclk_voltage_dependency_table()
HDsmu7_hwmgr.h104 struct smu7_single_dpm_table sclk_table; member
HDsmu8_hwmgr.c1512 struct phm_clock_voltage_dependency_table *sclk_table = in smu8_print_clock_levels() local
1524 for (i = 0; i < sclk_table->count; i++) in smu8_print_clock_levels()
1526 i, sclk_table->entries[i].clk / 100, in smu8_print_clock_levels()
HDvega10_hwmgr.c4246 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_print_clock_levels() local
4261 for (i = 0; i < sclk_table->count; i++) in vega10_print_clock_levels()
4263 i, sclk_table->dpm_levels[i].value / 100, in vega10_print_clock_levels()
4499 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_get_sclk_od() local
4504 value = (sclk_table->dpm_levels[sclk_table->count - 1].value - in vega10_get_sclk_od()
HDvega12_hwmgr.c2242 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2247 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
HDvegam_smumgr.c888 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
891 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
909 (uint8_t)dpm_table->sclk_table.count; in vegam_populate_all_graphic_levels()
911 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in vegam_populate_all_graphic_levels()
913 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
922 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
947 for (i = 2; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
1298 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in vegam_program_memory_timing_parameters()
1301 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in vegam_program_memory_timing_parameters()
1385 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in vegam_populate_smc_boot_level()
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HDpolaris10_smumgr.c1000 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1003 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
1018 (uint8_t)dpm_table->sclk_table.count; in polaris10_populate_all_graphic_levels()
1020 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in polaris10_populate_all_graphic_levels()
1028 for (i = 0; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1053 for (i = 2; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1368 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in polaris10_program_memory_timing_parameters()
1371 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in polaris10_program_memory_timing_parameters()
1457 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in polaris10_populate_smc_boot_level()
1517 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = in polaris10_populate_clock_stretcher_data_table() local
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HDtonga_smumgr.c700 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
702 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
716 if (dpm_table->sclk_table.count > 1) in tonga_populate_all_graphic_levels()
717 … smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in tonga_populate_all_graphic_levels()
721 (uint8_t)dpm_table->sclk_table.count; in tonga_populate_all_graphic_levels()
723 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in tonga_populate_all_graphic_levels()
730 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
760 for (i = 2; i < dpm_table->sclk_table.count; i++) in tonga_populate_all_graphic_levels()
1487 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in tonga_program_memory_timing_parameters()
1490 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in tonga_program_memory_timing_parameters()
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HDfiji_smumgr.c1036 for (i = 0; i < dpm_table->sclk_table.count; i++) { in fiji_populate_all_graphic_levels()
1038 dpm_table->sclk_table.dpm_levels[i].value, in fiji_populate_all_graphic_levels()
1052 levels[dpm_table->sclk_table.count - 1].DisplayWatermark = in fiji_populate_all_graphic_levels()
1056 (uint8_t)dpm_table->sclk_table.count; in fiji_populate_all_graphic_levels()
1058 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in fiji_populate_all_graphic_levels()
1065 for (i = 0; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1090 for (i = 2; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1329 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1546 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in fiji_program_memory_timing_parameters()
1549 data->dpm_table.sclk_table.dpm_levels[i].value, in fiji_program_memory_timing_parameters()
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HDiceland_smumgr.c980 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
996 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
997 … smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels()
1001 (uint8_t)dpm_table->sclk_table.count; in iceland_populate_all_graphic_levels()
1003 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in iceland_populate_all_graphic_levels()
1026 for (i = 2; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
1620 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in iceland_program_memory_timing_parameters()
1623 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in iceland_program_memory_timing_parameters()
1656 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in iceland_populate_smc_boot_level()
HDci_smumgr.c484 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
486 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
492 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
499 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
501 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
1657 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in ci_program_memory_timing_parameters()
1660 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters()
1693 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in ci_populate_smc_boot_level()
/dragonfly/sys/dev/drm/radeon/
HDci_dpm.c2589 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2592 … pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
3323 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
3325 … dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3332 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
3338 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3340 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
3498 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3513 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3516 … (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
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HDci_dpm.h68 struct ci_single_dpm_table sclk_table; member