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Searched refs:scl_data (Results 1 – 15 of 15) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
HDdcn10_dpp_dscl.c294 const struct scaler_data *scl_data, in dpp1_dscl_set_scl_filter() argument
301 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz; in dpp1_dscl_set_scl_filter()
302 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert; in dpp1_dscl_set_scl_filter()
309 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 in dpp1_dscl_set_scl_filter()
310 && scl_data->taps.h_taps_c < 3 in dpp1_dscl_set_scl_filter()
311 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp1_dscl_set_scl_filter()
312 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3 in dpp1_dscl_set_scl_filter()
313 && scl_data->taps.v_taps_c < 3 in dpp1_dscl_set_scl_filter()
314 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); in dpp1_dscl_set_scl_filter()
331 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp1_dscl_set_scl_filter()
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HDdcn10_dpp.c139 struct scaler_data *scl_data, in dpp_get_optimal_number_of_taps() argument
144 if (scl_data->viewport.width > scl_data->recout.width) in dpp_get_optimal_number_of_taps()
145 pixel_width = scl_data->recout.width; in dpp_get_optimal_number_of_taps()
147 pixel_width = scl_data->viewport.width; in dpp_get_optimal_number_of_taps()
150 if (scl_data->format == PIXEL_FORMAT_FP16 && in dpp_get_optimal_number_of_taps()
152 scl_data->ratios.horz.value != dc_fixpt_one.value && in dpp_get_optimal_number_of_taps()
153 scl_data->ratios.vert.value != dc_fixpt_one.value) in dpp_get_optimal_number_of_taps()
156 if (scl_data->viewport.width > scl_data->h_active && in dpp_get_optimal_number_of_taps()
158 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp_get_optimal_number_of_taps()
164 if (scl_data->ratios.horz.value == (4ll << 32)) in dpp_get_optimal_number_of_taps()
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HDdcn10_hw_sequencer.c1758 switch (pipe_ctx->plane_res.scl_data.format) { in dcn10_get_surface_visual_confirm_color()
1800 switch (top_pipe_ctx->plane_res.scl_data.format) { in dcn10_get_hdr_visual_confirm_color()
1997 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; in update_scaler()
1998 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; in update_scaler()
2001 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); in update_scaler()
2047 size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; in update_dchubp_dpp()
2069 &pipe_ctx->plane_res.scl_data.viewport, in update_dchubp_dpp()
2070 &pipe_ctx->plane_res.scl_data.viewport_c); in update_dchubp_dpp()
2604 .viewport = pipe_ctx->plane_res.scl_data.viewport, in dcn10_set_cursor_position()
2605 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, in dcn10_set_cursor_position()
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HDdcn10_dpp.h1359 struct scaler_data scl_data; member
1389 const struct scaler_data *scl_data,
1481 const struct scaler_data *scl_data);
/dragonfly/sys/dev/drm/amd/display/dc/dce/
HDdce_transform.c893 struct scaler_data *scl_data, in dce_transform_get_optimal_number_of_taps() argument
897 int pixel_width = scl_data->viewport.width; in dce_transform_get_optimal_number_of_taps()
901 (scl_data->viewport.width > scl_data->recout.width)) in dce_transform_get_optimal_number_of_taps()
902 pixel_width = scl_data->recout.width; in dce_transform_get_optimal_number_of_taps()
906 scl_data->lb_params.depth, in dce_transform_get_optimal_number_of_taps()
922 scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false); in dce_transform_get_optimal_number_of_taps()
923 scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false); in dce_transform_get_optimal_number_of_taps()
924 scl_data->taps.h_taps_c = decide_taps(scl_data->ratios.horz_c, in_taps->h_taps, true); in dce_transform_get_optimal_number_of_taps()
925 scl_data->taps.v_taps_c = decide_taps(scl_data->ratios.vert_c, in_taps->v_taps, true); in dce_transform_get_optimal_number_of_taps()
927 if (!IDENTITY_RATIO(scl_data->ratios.vert)) { in dce_transform_get_optimal_number_of_taps()
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HDdce_transform.h494 struct scaler_data *scl_data,
/dragonfly/sys/dev/drm/amd/display/dc/core/
HDdc_resource.c479 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; in calculate_viewport()
577 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x; in calculate_recout()
579 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x in calculate_recout()
583 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width * in calculate_recout()
585 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x > in calculate_recout()
587 pipe_ctx->plane_res.scl_data.recout.width = in calculate_recout()
589 - pipe_ctx->plane_res.scl_data.recout.x; in calculate_recout()
591 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y; in calculate_recout()
593 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y in calculate_recout()
597 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height * in calculate_recout()
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HDdc.c356 pipes->plane_res.scl_data.lb_params.depth, in dc_stream_set_dither_option()
/dragonfly/sys/dev/drm/amd/display/dc/calcs/
HDdcn_calcs.c277 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
278 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; in pipe_ctx_to_e2e_pipe_params()
279 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
280 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
374 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
375 … input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
376 … input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
377 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
380 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params()
381 input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c; in pipe_ctx_to_e2e_pipe_params()
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HDdce_calcs.c2796 … data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data()
2798 … data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); in populate_initial_data()
2799 … data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2800 … data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); in populate_initial_data()
2801 …cale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value… in populate_initial_data()
2802 …cale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value… in populate_initial_data()
2850 …t[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height); in populate_initial_data()
2851 …th[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width); in populate_initial_data()
2854 …_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps); in populate_initial_data()
2855 …_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps); in populate_initial_data()
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/dragonfly/sys/dev/drm/amd/display/dc/dce110/
HDdce110_transform_v.c48 const struct scaler_data *scl_data, in calculate_viewport() argument
53 luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2; in calculate_viewport()
54 luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2; in calculate_viewport()
56 scl_data->viewport.width - scl_data->viewport.width % 2; in calculate_viewport()
58 scl_data->viewport.height - scl_data->viewport.height % 2; in calculate_viewport()
64 if (scl_data->format == PIXEL_FORMAT_420BPP8) { in calculate_viewport()
HDdce110_hw_sequencer.c1226 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
1276 pipe_ctx->plane_res.scl_data.lb_params.depth, in program_scaler()
1294 &pipe_ctx->plane_res.scl_data); in program_scaler()
1457 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in apply_single_controller_ctx_to_hw()
2117 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; in set_default_colors()
2124 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; in set_default_colors()
2649 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in dce110_program_front_end_for_pipe()
2717 pipe_ctx->plane_res.scl_data.viewport.width, in dce110_program_front_end_for_pipe()
2718 pipe_ctx->plane_res.scl_data.viewport.height, in dce110_program_front_end_for_pipe()
2719 pipe_ctx->plane_res.scl_data.viewport.x, in dce110_program_front_end_for_pipe()
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/dragonfly/sys/dev/drm/amd/display/dc/inc/hw/
HDtransform.h188 const struct scaler_data *scl_data);
197 struct scaler_data *scl_data,
299 const struct scaler_data *scl_data,
HDdpp.h67 const struct scaler_data *scl_data);
76 struct scaler_data *scl_data,
/dragonfly/sys/dev/drm/amd/display/dc/inc/
HDcore_types.h198 struct scaler_data scl_data; member