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Searched refs:reg_data (Results 1 – 12 of 12) sorted by relevance

/dragonfly/sys/dev/netif/ig_hal/
HDe1000_80003es2lan.c887 u32 reg_data; in e1000_init_hw_80003es2lan() local
934 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); in e1000_init_hw_80003es2lan()
935 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_80003es2lan()
937 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); in e1000_init_hw_80003es2lan()
940 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); in e1000_init_hw_80003es2lan()
941 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_80003es2lan()
943 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); in e1000_init_hw_80003es2lan()
946 reg_data = E1000_READ_REG(hw, E1000_TCTL); in e1000_init_hw_80003es2lan()
947 reg_data |= E1000_TCTL_RTLC; in e1000_init_hw_80003es2lan()
948 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); in e1000_init_hw_80003es2lan()
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HDe1000_82571.c1187 u32 reg_data; in e1000_init_hw_82571() local
1223 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); in e1000_init_hw_82571()
1224 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_82571()
1226 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); in e1000_init_hw_82571()
1235 reg_data = E1000_READ_REG(hw, E1000_GCR); in e1000_init_hw_82571()
1236 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; in e1000_init_hw_82571()
1237 E1000_WRITE_REG(hw, E1000_GCR, reg_data); in e1000_init_hw_82571()
1240 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); in e1000_init_hw_82571()
1241 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_82571()
1244 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); in e1000_init_hw_82571()
HDe1000_ich8lan.c2265 u16 word_addr, reg_data, reg_addr, phy_page = 0; in e1000_sw_lcd_config_ich8lan() local
2348 &reg_data); in e1000_sw_lcd_config_ich8lan()
2359 phy_page = reg_data; in e1000_sw_lcd_config_ich8lan()
2367 reg_data); in e1000_sw_lcd_config_ich8lan()
5301 u16 reg_data; in e1000_setup_copper_link_ich8lan() local
5320 &reg_data); in e1000_setup_copper_link_ich8lan()
5323 reg_data |= 0x3F; in e1000_setup_copper_link_ich8lan()
5326 reg_data); in e1000_setup_copper_link_ich8lan()
5350 &reg_data); in e1000_setup_copper_link_ich8lan()
5354 reg_data &= ~IFE_PMC_AUTO_MDIX; in e1000_setup_copper_link_ich8lan()
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/dragonfly/sys/dev/drm/amd/display/modules/stats/
HDstats.c115 unsigned int reg_data; in mod_stats_create() local
131 &reg_data, sizeof(unsigned int), &flag)) in mod_stats_create()
132 core_stats->enabled = reg_data; in mod_stats_create()
138 &reg_data, sizeof(unsigned int), &flag)) { in mod_stats_create()
139 if (reg_data > DAL_STATS_ENTRIES_REGKEY_MAX) in mod_stats_create()
142 core_stats->entries = reg_data; in mod_stats_create()
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
HDdce110_compressor.c276 uint32_t reg_data; in dce110_compressor_disable_fbc() local
278 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); in dce110_compressor_disable_fbc()
279 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN); in dce110_compressor_disable_fbc()
280 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data); in dce110_compressor_disable_fbc()
HDdce110_transform_v.c634 uint32_t reg_data = 0; in dce110_xfmv_set_pixel_storage_depth() local
659 reg_data, in dce110_xfmv_set_pixel_storage_depth()
665 reg_data, in dce110_xfmv_set_pixel_storage_depth()
670 dm_write_reg(xfm->ctx, mmLBV_DATA_FORMAT, reg_data); in dce110_xfmv_set_pixel_storage_depth()
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
HDsmu8_smumgr.c175 uint32_t reg_data; in smu8_load_mec_firmware() local
207 reg_data = lower_32_bits(info.mc_addr) & in smu8_load_mec_firmware()
209 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data); in smu8_load_mec_firmware()
211 reg_data = upper_32_bits(info.mc_addr) & in smu8_load_mec_firmware()
213 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data); in smu8_load_mec_firmware()
/dragonfly/sys/dev/drm/amd/display/dc/dce112/
HDdce112_compressor.c420 uint32_t reg_data; in dce112_compressor_disable_fbc() local
422 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); in dce112_compressor_disable_fbc()
423 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN); in dce112_compressor_disable_fbc()
424 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data); in dce112_compressor_disable_fbc()
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
HDppatomctrl.c55 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) in atomctrl_retrieve_ac_timing() local
60 while (*(uint32_t *)reg_data != END_OF_REG_DATA_BLOCK && in atomctrl_retrieve_ac_timing()
62 tmem_id = (uint8_t)((*(uint32_t *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT); in atomctrl_retrieve_ac_timing()
66 (uint32_t)((*(uint32_t *)reg_data & CLOCK_RANGE_MASK) >> in atomctrl_retrieve_ac_timing()
73 (uint32_t)*((uint32_t *)reg_data + j); in atomctrl_retrieve_ac_timing()
84 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) in atomctrl_retrieve_ac_timing()
85 ((uint8_t *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)) ; in atomctrl_retrieve_ac_timing()
88 PP_ASSERT_WITH_CODE((*(uint32_t *)reg_data == END_OF_REG_DATA_BLOCK), in atomctrl_retrieve_ac_timing()
/dragonfly/sys/dev/drm/amd/display/dc/dce/
HDdce_audio.c57 uint32_t reg_data) in write_indirect_azalia_reg() argument
67 AZALIA_ENDPOINT_REG_DATA, reg_data); in write_indirect_azalia_reg()
70 reg_index, reg_data); in write_indirect_azalia_reg()
/dragonfly/sys/dev/drm/amd/amdgpu/
HDamdgpu_atombios.c1593 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = in amdgpu_atombios_init_mc_reg_table() local
1614 … while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && in amdgpu_atombios_init_mc_reg_table()
1616 … t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) in amdgpu_atombios_init_mc_reg_table()
1620 … (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) in amdgpu_atombios_init_mc_reg_table()
1625 … (u32)le32_to_cpu(*((u32 *)reg_data + j)); in amdgpu_atombios_init_mc_reg_table()
1634 … reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) in amdgpu_atombios_init_mc_reg_table()
1635 … ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); in amdgpu_atombios_init_mc_reg_table()
1637 … if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) in amdgpu_atombios_init_mc_reg_table()
/dragonfly/sys/dev/drm/radeon/
HDradeon_atombios.c3991 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = in radeon_atom_init_mc_reg_table() local
4012 … while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && in radeon_atom_init_mc_reg_table()
4014 … t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) in radeon_atom_init_mc_reg_table()
4018 … (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) in radeon_atom_init_mc_reg_table()
4023 … (u32)le32_to_cpu(*((u32 *)reg_data + j)); in radeon_atom_init_mc_reg_table()
4032 … reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) in radeon_atom_init_mc_reg_table()
4033 … ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); in radeon_atom_init_mc_reg_table()
4035 … if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) in radeon_atom_init_mc_reg_table()