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Searched refs:pptable (Results 1 – 17 of 17) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
HDprocess_pptables_v1_0.c209 (struct phm_ppt_v1_information *)(hwmgr->pptable); in get_platform_power_management_table()
252 …t phm_ppt_v1_information *pp_table_information = (struct phm_ppt_v1_information *)(hwmgr->pptable); in init_dpm_2_parameters()
500 (struct phm_ppt_v1_information *)(hwmgr->pptable); in get_pcie_table()
738 (struct phm_ppt_v1_information *)(hwmgr->pptable); in get_gpio_table()
770 (struct phm_ppt_v1_information *)(hwmgr->pptable); in init_clock_voltage_dependency()
1065 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v1_information), GFP_KERNEL); in pp_tables_v1_0_initialize()
1067 PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable), in pp_tables_v1_0_initialize()
1070 memset(hwmgr->pptable, 0x00, sizeof(struct phm_ppt_v1_information)); in pp_tables_v1_0_initialize()
1114 (struct phm_ppt_v1_information *)(hwmgr->pptable); in pp_tables_v1_0_uninitialize()
1152 kfree(hwmgr->pptable); in pp_tables_v1_0_uninitialize()
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HDvega12_processpptables.c240 (struct phm_ppt_v3_information *)hwmgr->pptable; in init_powerplay_table_information()
308 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL); in vega12_pp_tables_initialize()
309 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), in vega12_pp_tables_initialize()
335 (struct phm_ppt_v3_information *)(hwmgr->pptable); in vega12_pp_tables_uninitialize()
352 kfree(hwmgr->pptable); in vega12_pp_tables_uninitialize()
353 hwmgr->pptable = NULL; in vega12_pp_tables_uninitialize()
HDvega10_hwmgr.c180 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_set_features_platform_caps()
290 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_odn_initial_default_setting()
498 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_get_socclk_for_voltage_evv()
535 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_get_evv_voltages()
640 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_patch_voltage_dependency_tables_with_lookup_table()
718 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_complete_dependency_tables()
747 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_set_private_data_based_on_pptable()
1133 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_construct_voltage_tables()
1222 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_setup_default_pcie_table()
1270 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_setup_default_dpm_tables()
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HDvega10_processpptables.c764 (struct phm_ppt_v2_information *)(hwmgr->pptable); in get_pcie_table()
859 (struct phm_ppt_v2_information *)(hwmgr->pptable); in init_powerplay_extended_tables()
1051 (struct phm_ppt_v2_information *)(hwmgr->pptable); in init_dpm_2_parameters()
1139 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL); in vega10_pp_tables_initialize()
1141 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), in vega10_pp_tables_initialize()
1186 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_pp_tables_uninitialize()
1224 kfree(hwmgr->pptable); in vega10_pp_tables_uninitialize()
1225 hwmgr->pptable = NULL; in vega10_pp_tables_uninitialize()
HDsmu7_hwmgr.c252 (struct phm_ppt_v1_information *)hwmgr->pptable; in smu7_construct_voltage_tables()
529 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_setup_default_pcie_table()
756 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_setup_dpm_tables_v1()
822 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_odn_initial_default_setting()
867 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_setup_voltage_range_from_vbios()
895 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_check_dpm_table_updated()
1557 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_init_dpm_defaults()
1706 (struct phm_ppt_v1_information *)hwmgr->pptable; in smu7_get_evv_voltages()
1839 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_patch_clock_voltage_limits_with_vddc_leakage()
1853 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_patch_voltage_dependency_tables_with_lookup_table()
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HDsmu_helper.c419 (struct phm_ppt_v1_information *)(hwmgr->pptable); in phm_get_sclk_for_voltage_evv()
449 … struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); in phm_initializa_dynamic_state_adjustment_rule_settings()
489 (struct phm_ppt_v1_information *)hwmgr->pptable; in phm_apply_dal_min_voltage_request()
HDvega12_thermal.c174 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega12_thermal_set_temperature_range()
HDsmu10_hwmgr.c387 struct smu10_voltage_dependency_table **pptable, in smu10_get_clock_voltage_dependency_table() argument
407 *pptable = ptable; in smu10_get_clock_voltage_dependency_table()
HDvega10_thermal.c366 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_thermal_set_temperature_range()
HDvega10_powertune.c1292 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_initialize_power_tune_defaults()
1342 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_enable_power_containment()
HDvega12_hwmgr.c726 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega12_init_smc_table()
1599 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega12_get_dal_power_level()
2316 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega12_get_thermal_temperature_range()
HDsmu7_powertune.c1113 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_enable_power_containment()
1198 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_power_control_set_level()
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
HDvegam_smumgr.c337 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_update_uvd_smc_table()
369 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_update_vce_smc_table()
400 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_update_bif_smc_table()
435 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_initialize_power_tune_defaults()
507 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_cac_table()
544 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_ulv_level()
817 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_single_graphic_level()
870 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_all_graphic_levels()
986 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_single_memory_level()
1089 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_mvdd_value()
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HDpolaris10_smumgr.c430 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_bapm_parameters_in_dpm_table()
489 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_tdc_limit()
569 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_bapm_vddc_base_leakage_sidd()
704 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_cac_table()
738 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_ulv_level()
913 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_single_graphic_level()
982 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_all_graphic_levels()
1075 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_single_memory_level()
1177 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_mvdd_value()
1204 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_smc_acpi_level()
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HDfiji_smumgr.c483 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_initialize_power_tune_defaults()
505 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_bapm_parameters_in_dpm_table()
599 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_tdc_limit()
685 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_bapm_vddc_base_leakage_sidd()
773 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_cac_table()
813 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_ulv_level()
956 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_single_graphic_level()
1020 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_all_graphic_levels()
1180 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_single_memory_level()
1289 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_mvdd_value()
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HDtonga_smumgr.c243 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_get_dependency_volt_by_clk()
388 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_cac_tables()
473 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_ulv_level()
614 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_single_graphic_level()
680 … struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_all_graphic_levels()
957 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_single_memory_level()
1138 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_mvdd_value()
1306 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_smc_uvd_level()
1366 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_smc_vce_level()
1411 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_smc_acp_level()
[all …]
/dragonfly/sys/dev/drm/amd/powerplay/inc/
HDhwmgr.h729 void *pptable; member