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Searched refs:pll1 (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/i915/
HDintel_dpll_mgr.h136 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, member
HDintel_dpll_mgr.c1474 temp |= pll->state.hw_state.pll1; in bxt_ddi_pll_enable()
1601 hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1)); in bxt_ddi_pll_get_hw_state()
1602 hw_state->pll1 &= PORT_PLL_N_MASK; in bxt_ddi_pll_get_hw_state()
1757 dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n); in bxt_ddi_set_dpll_hw_state()
1859 hw_state->pll1, in bxt_dump_hw_state()
HDintel_ddi.c1469 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; in bxt_calc_pll_link()
HDintel_display.c11299 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); in intel_pipe_config_compare()