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Searched refs:plane_res (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/core/
HDdc_resource.c479 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; in calculate_viewport()
577 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x; in calculate_recout()
579 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x in calculate_recout()
583 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width * in calculate_recout()
585 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x > in calculate_recout()
587 pipe_ctx->plane_res.scl_data.recout.width = in calculate_recout()
589 - pipe_ctx->plane_res.scl_data.recout.x; in calculate_recout()
591 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y; in calculate_recout()
593 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y in calculate_recout()
597 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height * in calculate_recout()
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HDdc_stream.c254 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || in dc_stream_set_cursor_position()
256 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || in dc_stream_set_cursor_position()
257 !pipe_ctx->plane_res.ipp) in dc_stream_set_cursor_position()
HDdc.c352 if (pipes->plane_res.xfm && in dc_stream_set_dither_option()
353 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) { in dc_stream_set_dither_option()
354 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in dc_stream_set_dither_option()
355 pipes->plane_res.xfm, in dc_stream_set_dither_option()
356 pipes->plane_res.scl_data.lb_params.depth, in dc_stream_set_dither_option()
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
HDdce110_hw_sequencer.c270 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; in dce110_set_input_transfer_func()
598 struct transform *xfm = pipe_ctx->plane_res.xfm; in dce110_set_output_transfer_func()
1226 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
1263 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) in program_scaler()
1274 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in program_scaler()
1275 pipe_ctx->plane_res.xfm, in program_scaler()
1276 pipe_ctx->plane_res.scl_data.lb_params.depth, in program_scaler()
1293 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in program_scaler()
1294 &pipe_ctx->plane_res.scl_data); in program_scaler()
1457 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in apply_single_controller_ctx_to_hw()
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HDdce110_resource.c982 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; in dce110_acquire_underlay()
984 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; in dce110_acquire_underlay()
1013 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, in dce110_acquire_underlay()
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
HDdcn10_hw_sequencer.c770 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
795 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
808 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
818 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
830 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
861 struct hubp *hubp = pipe_ctx->plane_res.hubp; in hwss1_plane_atomic_disconnect()
862 int dpp_id = pipe_ctx->plane_res.dpp->inst; in hwss1_plane_atomic_disconnect()
877 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in hwss1_plane_atomic_disconnect()
891 struct dpp *dpp = pipe_ctx->plane_res.dpp; in plane_atomic_power_down()
898 hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false); in plane_atomic_power_down()
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HDdcn10_resource.c1042 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1043 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1044 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1045 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn10_acquire_idle_pipe_for_layer()
/dragonfly/sys/dev/drm/amd/display/dc/calcs/
HDdcn_calcs.c254 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
269 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
277 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
278 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; in pipe_ctx_to_e2e_pipe_params()
279 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
280 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
374 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
375 … input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
376 … input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
377 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
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HDdce_calcs.c2796 … data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data()
2798 … data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); in populate_initial_data()
2799 … data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2800 … data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); in populate_initial_data()
2801 …data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.h… in populate_initial_data()
2802 …data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.v… in populate_initial_data()
2850 …src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewpor… in populate_initial_data()
2851 …>src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewpor… in populate_initial_data()
2854 …ta->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_… in populate_initial_data()
2855 …ta->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_… in populate_initial_data()
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/dragonfly/sys/dev/drm/amd/display/dc/inc/
HDcore_types.h213 struct plane_resource plane_res; member
/dragonfly/sys/dev/drm/amd/display/dc/dce/
HDdce_clocks.c554 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( in dcn1_ramp_up_dispclk_with_dpp()
555 pipe_ctx->plane_res.dpp, in dcn1_ramp_up_dispclk_with_dpp()