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Searched refs:nvm_data (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/netif/iwm/
HDif_iwm_util.h135 return sc->nvm_data && sc->nvm_data->valid_tx_ant ? in iwm_get_valid_tx_ant()
136 sc->sc_fw.valid_tx_ant & sc->nvm_data->valid_tx_ant : in iwm_get_valid_tx_ant()
143 return sc->nvm_data && sc->nvm_data->valid_rx_ant ? in iwm_get_valid_rx_ant()
144 sc->sc_fw.valid_rx_ant & sc->nvm_data->valid_rx_ant : in iwm_get_valid_rx_ant()
HDif_iwmvar.h486 struct iwm_nvm_data *nvm_data; member
HDif_iwm.c1992 const uint16_t * const nvm_ch_flags = sc->nvm_data->nvm_ch_flags; in iwm_add_channel_band()
2033 struct iwm_nvm_data *data = sc->nvm_data; in iwm_init_channel_map()
2381 sc->nvm_data = iwm_parse_nvm_sections(sc, nvm_sections); in iwm_nvm_init()
2382 if (!sc->nvm_data) in iwm_nvm_init()
2385 "nvm version = %x\n", sc->nvm_data->nvm_version); in iwm_nvm_init()
2983 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, sc->nvm_data->hw_addr); in iwm_run_init_ucode()
4694 boolean_t nvm_lar = sc->nvm_data->lar_enabled; in iwm_is_lar_supported()
6389 sc->sc_fwver, ether_sprintf(sc->nvm_data->hw_addr)); in iwm_preinit()
6392 if (!sc->nvm_data->sku_cap_band_52GHz_enable) in iwm_preinit()
6688 iwm_free_nvm_data(sc->nvm_data); in iwm_detach_local()
HDif_iwm_scan.c430 if (sc->nvm_data->sku_cap_band_52GHz_enable) { in iwm_fill_probe_req()
/dragonfly/sys/dev/netif/ig_hal/
HDe1000_82540.c502 u16 nvm_data; in e1000_adjust_serdes_amplitude_82540() local
506 ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data); in e1000_adjust_serdes_amplitude_82540()
510 if (nvm_data != NVM_RESERVED_WORD) { in e1000_adjust_serdes_amplitude_82540()
512 nvm_data &= NVM_SERDES_AMPLITUDE_MASK; in e1000_adjust_serdes_amplitude_82540()
514 nvm_data); in e1000_adjust_serdes_amplitude_82540()
591 u16 nvm_data; in e1000_set_phy_mode_82540() local
598 ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data); in e1000_set_phy_mode_82540()
604 if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) { in e1000_set_phy_mode_82540()
694 u16 offset, nvm_data, i; in e1000_read_mac_addr_82540() local
700 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); in e1000_read_mac_addr_82540()
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HDe1000_nvm.c778 u16 nvm_data; in e1000_read_pba_string_generic() local
796 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); in e1000_read_pba_string_generic()
812 if (nvm_data != NVM_PBA_PTR_GUARD) { in e1000_read_pba_string_generic()
822 pba_num[0] = (nvm_data >> 12) & 0xF; in e1000_read_pba_string_generic()
823 pba_num[1] = (nvm_data >> 8) & 0xF; in e1000_read_pba_string_generic()
824 pba_num[2] = (nvm_data >> 4) & 0xF; in e1000_read_pba_string_generic()
825 pba_num[3] = nvm_data & 0xF; in e1000_read_pba_string_generic()
868 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data); in e1000_read_pba_string_generic()
873 pba_num[offset * 2] = (u8)(nvm_data >> 8); in e1000_read_pba_string_generic()
874 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); in e1000_read_pba_string_generic()
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HDe1000_82542.c571 u16 offset, nvm_data, i; in e1000_read_mac_addr_82542() local
577 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); in e1000_read_mac_addr_82542()
582 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); in e1000_read_mac_addr_82542()
583 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); in e1000_read_mac_addr_82542()
HDe1000_82575.c2426 u16 nvm_data = 0; in e1000_reset_mdicnfg_82580() local
2437 &nvm_data); in e1000_reset_mdicnfg_82580()
2444 if (nvm_data & NVM_WORD24_EXT_MDIO) in e1000_reset_mdicnfg_82580()
2446 if (nvm_data & NVM_WORD24_COM_MDIO) in e1000_reset_mdicnfg_82580()
2583 u16 i, nvm_data; in e1000_validate_nvm_checksum_with_offset() local
2588 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); in e1000_validate_nvm_checksum_with_offset()
2593 checksum += nvm_data; in e1000_validate_nvm_checksum_with_offset()
2620 u16 i, nvm_data; in e1000_update_nvm_checksum_with_offset() local
2625 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); in e1000_update_nvm_checksum_with_offset()
2630 checksum += nvm_data; in e1000_update_nvm_checksum_with_offset()
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HDe1000_mac.c411 u16 offset, nvm_alt_mac_addr_offset, nvm_data; in e1000_check_alt_mac_addr_generic() local
416 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); in e1000_check_alt_mac_addr_generic()
450 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); in e1000_check_alt_mac_addr_generic()
456 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); in e1000_check_alt_mac_addr_generic()
457 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); in e1000_check_alt_mac_addr_generic()
956 u16 nvm_data; in e1000_set_default_fc_generic() local
974 1, &nvm_data); in e1000_set_default_fc_generic()
978 1, &nvm_data); in e1000_set_default_fc_generic()
987 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) in e1000_set_default_fc_generic()
989 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == in e1000_set_default_fc_generic()
HDe1000_i210.c640 u16 i, nvm_data; in e1000_update_nvm_checksum_i210() local
649 ret_val = e1000_read_nvm_eerd(hw, 0, 1, &nvm_data); in e1000_update_nvm_checksum_i210()
663 ret_val = e1000_read_nvm_eerd(hw, i, 1, &nvm_data); in e1000_update_nvm_checksum_i210()
669 checksum += nvm_data; in e1000_update_nvm_checksum_i210()