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Searched refs:mmVM_L2_CNTL4 (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfxhub_v1_0.c160 WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp); in gfxhub_v1_0_init_cache_regs()
HDgmc_v8_0.c871 tmp = RREG32(mmVM_L2_CNTL4); in gmc_v8_0_gart_enable()
884 WREG32(mmVM_L2_CNTL4, tmp); in gmc_v8_0_gart_enable()
HDmmhub_v1_0.c172 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp); in mmhub_v1_0_init_cache_regs()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gmc/
HDgmc_8_2_d.h657 #define mmVM_L2_CNTL4 0x578 macro
HDgmc_8_1_d.h655 #define mmVM_L2_CNTL4 0x578 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/mmhub/
HDmmhub_9_1_offset.h1340 #define mmVM_L2_CNTL4 … macro
HDmmhub_1_0_offset.h1308 #define mmVM_L2_CNTL4 … macro
HDmmhub_9_3_0_offset.h1324 #define mmVM_L2_CNTL4 … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h1186 #define mmVM_L2_CNTL4 … macro
HDgc_9_2_1_offset.h1168 #define mmVM_L2_CNTL4 … macro
HDgc_9_1_offset.h1230 #define mmVM_L2_CNTL4 … macro