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Searched refs:mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDgmc_v7_0.c444 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; in gmc_v7_0_emit_flush_gpu_tlb()
645 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); in gmc_v7_0_gart_enable()
668 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, in gmc_v7_0_gart_enable()
HDgmc_v8_0.c647 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; in gmc_v8_0_emit_flush_gpu_tlb()
888 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); in gmc_v8_0_gart_enable()
911 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, in gmc_v8_0_gart_enable()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gmc/
HDgmc_7_0_d.h580 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f macro
HDgmc_8_2_d.h638 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f macro
HDgmc_6_0_d.h1219 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x054F macro
HDgmc_7_1_d.h613 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f macro
HDgmc_8_1_d.h636 #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f macro