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Searched refs:mmTC_CFG_L2_LOAD_POLICY1 (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_0_d.h2128 #define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e macro
HDgfx_7_2_d.h2149 #define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e macro
HDgfx_8_0_d.h2341 #define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e macro
HDgfx_8_1_d.h2320 #define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h1700 #define mmTC_CFG_L2_LOAD_POLICY1 … macro
HDgc_9_2_1_offset.h1954 #define mmTC_CFG_L2_LOAD_POLICY1 … macro
HDgc_9_1_offset.h2014 #define mmTC_CFG_L2_LOAD_POLICY1 … macro