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Searched refs:mmSQ_PERFCOUNTER_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_0_d.h1794 #define mmSQ_PERFCOUNTER_MASK 0xd9e1 macro
HDgfx_7_2_d.h1815 #define mmSQ_PERFCOUNTER_MASK 0xd9e1 macro
HDgfx_8_0_d.h2013 #define mmSQ_PERFCOUNTER_MASK 0xd9e1 macro
HDgfx_8_1_d.h1981 #define mmSQ_PERFCOUNTER_MASK 0xd9e1 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h5667 #define mmSQ_PERFCOUNTER_MASK … macro
HDgc_9_2_1_offset.h5914 #define mmSQ_PERFCOUNTER_MASK … macro
HDgc_9_1_offset.h5954 #define mmSQ_PERFCOUNTER_MASK … macro