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Searched refs:mmSQ_PERFCOUNTER5_SELECT (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h1485 #define mmSQ_PERFCOUNTER5_SELECT 0x2345 macro
HDgfx_7_0_d.h1835 #define mmSQ_PERFCOUNTER5_SELECT 0xd9c5 macro
HDgfx_7_2_d.h1856 #define mmSQ_PERFCOUNTER5_SELECT 0xd9c5 macro
HDgfx_8_0_d.h2054 #define mmSQ_PERFCOUNTER5_SELECT 0xd9c5 macro
HDgfx_8_1_d.h2022 #define mmSQ_PERFCOUNTER5_SELECT 0xd9c5 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h5643 #define mmSQ_PERFCOUNTER5_SELECT … macro
HDgc_9_2_1_offset.h5890 #define mmSQ_PERFCOUNTER5_SELECT … macro
HDgc_9_1_offset.h5930 #define mmSQ_PERFCOUNTER5_SELECT … macro