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Searched refs:mmSPI_PS_INPUT_CNTL_29 (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h1242 #define mmSPI_PS_INPUT_CNTL_29 0xA1AE macro
HDgfx_7_0_d.h1390 #define mmSPI_PS_INPUT_CNTL_29 0xa1ae macro
HDgfx_7_2_d.h1407 #define mmSPI_PS_INPUT_CNTL_29 0xa1ae macro
HDgfx_8_0_d.h1586 #define mmSPI_PS_INPUT_CNTL_29 0xa1ae macro
HDgfx_8_1_d.h1554 #define mmSPI_PS_INPUT_CNTL_29 0xa1ae macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h3857 #define mmSPI_PS_INPUT_CNTL_29 … macro
HDgc_9_2_1_offset.h4096 #define mmSPI_PS_INPUT_CNTL_29 … macro
HDgc_9_1_offset.h4144 #define mmSPI_PS_INPUT_CNTL_29 … macro