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Searched refs:mmSPI_PS_INPUT_CNTL_19 (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h1231 #define mmSPI_PS_INPUT_CNTL_19 0xA1A4 macro
HDgfx_7_0_d.h1380 #define mmSPI_PS_INPUT_CNTL_19 0xa1a4 macro
HDgfx_7_2_d.h1397 #define mmSPI_PS_INPUT_CNTL_19 0xa1a4 macro
HDgfx_8_0_d.h1576 #define mmSPI_PS_INPUT_CNTL_19 0xa1a4 macro
HDgfx_8_1_d.h1544 #define mmSPI_PS_INPUT_CNTL_19 0xa1a4 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h3837 #define mmSPI_PS_INPUT_CNTL_19 … macro
HDgc_9_2_1_offset.h4076 #define mmSPI_PS_INPUT_CNTL_19 … macro
HDgc_9_1_offset.h4124 #define mmSPI_PS_INPUT_CNTL_19 … macro