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Searched refs:mmSPI_COMPUTE_QUEUE_RESET (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_0_d.h1430 #define mmSPI_COMPUTE_QUEUE_RESET 0x31db macro
HDgfx_7_2_d.h1447 #define mmSPI_COMPUTE_QUEUE_RESET 0x31db macro
HDgfx_8_0_d.h1626 #define mmSPI_COMPUTE_QUEUE_RESET 0x31db macro
HDgfx_8_1_d.h1594 #define mmSPI_COMPUTE_QUEUE_RESET 0x31db macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h2669 #define mmSPI_COMPUTE_QUEUE_RESET … macro
HDgc_9_2_1_offset.h2910 #define mmSPI_COMPUTE_QUEUE_RESET … macro
HDgc_9_1_offset.h2954 #define mmSPI_COMPUTE_QUEUE_RESET … macro