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Searched refs:mmRLC_SRM_INDEX_CNTL_ADDR_4 (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_8_0_d.h1467 #define mmRLC_SRM_INDEX_CNTL_ADDR_4 0xec8f macro
HDgfx_8_1_d.h1463 #define mmRLC_SRM_INDEX_CNTL_ADDR_4 0xec8f macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h6105 #define mmRLC_SRM_INDEX_CNTL_ADDR_4 … macro
HDgc_9_2_1_offset.h6360 #define mmRLC_SRM_INDEX_CNTL_ADDR_4 … macro
HDgc_9_1_offset.h6384 #define mmRLC_SRM_INDEX_CNTL_ADDR_4 … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v9_0.c223 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,