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Searched refs:mmRLC_SRM_ARAM_DATA (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_8_0_d.h1456 #define mmRLC_SRM_ARAM_DATA 0xec84 macro
HDgfx_8_1_d.h1452 #define mmRLC_SRM_ARAM_DATA 0xec84 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h6083 #define mmRLC_SRM_ARAM_DATA … macro
HDgc_9_2_1_offset.h6338 #define mmRLC_SRM_ARAM_DATA … macro
HDgc_9_1_offset.h6362 #define mmRLC_SRM_ARAM_DATA … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v9_0.c1945 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), in gfx_v9_1_init_rlc_save_restore_list()
HDgfx_v8_0.c4082 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]); in gfx_v8_0_init_save_restore_list()