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Searched refs:mmRLC_LB_PARAMS (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h1152 #define mmRLC_LB_PARAMS 0x3109 macro
HDgfx_7_0_d.h1289 #define mmRLC_LB_PARAMS 0x3111 macro
HDgfx_7_2_d.h1302 #define mmRLC_LB_PARAMS 0x3111 macro
HDgfx_8_0_d.h1402 #define mmRLC_LB_PARAMS 0xec51 macro
HDgfx_8_1_d.h1402 #define mmRLC_LB_PARAMS 0xec51 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h5999 #define mmRLC_LB_PARAMS … macro
HDgc_9_2_1_offset.h6254 #define mmRLC_LB_PARAMS … macro
HDgc_9_1_offset.h6278 #define mmRLC_LB_PARAMS … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v9_0.c834 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); in gfx_v9_0_init_lbpw()