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Searched refs:mmRLC_GPU_CLOCK_32_RES_SEL (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h1144 #define mmRLC_GPU_CLOCK_32_RES_SEL 0x30D4 macro
HDgfx_7_0_d.h1273 #define mmRLC_GPU_CLOCK_32_RES_SEL 0x3101 macro
HDgfx_7_2_d.h1286 #define mmRLC_GPU_CLOCK_32_RES_SEL 0x3101 macro
HDgfx_8_0_d.h1384 #define mmRLC_GPU_CLOCK_32_RES_SEL 0xec41 macro
HDgfx_8_1_d.h1386 #define mmRLC_GPU_CLOCK_32_RES_SEL 0xec41 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h5971 #define mmRLC_GPU_CLOCK_32_RES_SEL … macro
HDgc_9_2_1_offset.h6226 #define mmRLC_GPU_CLOCK_32_RES_SEL … macro
HDgc_9_1_offset.h6250 #define mmRLC_GPU_CLOCK_32_RES_SEL … macro