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Searched refs:mmRLC_GPM_UCODE_ADDR (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDpsp_v10_0.c366 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); in psp_v10_0_sram_map()
HDpsp_v3_1.c499 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); in psp_v3_1_sram_map()
HDgfx_v9_0.c2271 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, in gfx_v9_0_rlc_load_microcode()
2275 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v9_0_rlc_load_microcode()
HDgfx_v8_0.c4219 WREG32(mmRLC_GPM_UCODE_ADDR, 0); in gfx_v8_0_rlc_load_microcode()
4222 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v8_0_rlc_load_microcode()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_0_d.h1266 #define mmRLC_GPM_UCODE_ADDR 0x30e2 macro
HDgfx_7_2_d.h1279 #define mmRLC_GPM_UCODE_ADDR 0x30e2 macro
HDgfx_8_0_d.h1374 #define mmRLC_GPM_UCODE_ADDR 0xf83c macro
HDgfx_8_1_d.h1377 #define mmRLC_GPM_UCODE_ADDR 0xf83c macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h6695 #define mmRLC_GPM_UCODE_ADDR macro
HDgc_9_2_1_offset.h7014 #define mmRLC_GPM_UCODE_ADDR macro
HDgc_9_1_offset.h6976 #define mmRLC_GPM_UCODE_ADDR macro