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Searched refs:mmPA_CL_UCP_1_W (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h816 #define mmPA_CL_UCP_1_W 0xA176 macro
HDgfx_7_0_d.h931 #define mmPA_CL_UCP_1_W 0xa176 macro
HDgfx_7_2_d.h944 #define mmPA_CL_UCP_1_W 0xa176 macro
HDgfx_8_0_d.h1026 #define mmPA_CL_UCP_1_W 0xa176 macro
HDgfx_8_1_d.h1026 #define mmPA_CL_UCP_1_W 0xa176 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h3765 #define mmPA_CL_UCP_1_W … macro
HDgc_9_2_1_offset.h4002 #define mmPA_CL_UCP_1_W … macro
HDgc_9_1_offset.h4052 #define mmPA_CL_UCP_1_W … macro