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Searched refs:mmMC_ARB_DRAM_TIMING_1 (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gmc/
HDgmc_7_0_d.h86 #define mmMC_ARB_DRAM_TIMING_1 0x9fc macro
HDgmc_8_2_d.h90 #define mmMC_ARB_DRAM_TIMING_1 0x9fc macro
HDgmc_6_0_d.h622 #define mmMC_ARB_DRAM_TIMING_1 0x09FC macro
HDgmc_7_1_d.h87 #define mmMC_ARB_DRAM_TIMING_1 0x9fc macro
HDgmc_8_1_d.h90 #define mmMC_ARB_DRAM_TIMING_1 0x9fc macro
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
HDsmu7_hwmgr.c460 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); in smu7_copy_and_switch_arb_sets()
475 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); in smu7_copy_and_switch_arb_sets()