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Searched refs:mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gmc/
HDgmc_8_2_d.h775 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x5eb8 macro
HDgmc_8_1_d.h1573 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x5eb8 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_offset.h1484 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_12_0_offset.h320 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL … macro