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Searched refs:mmGRBM_GFX_INDEX (Results 1 – 16 of 16) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDvce_v3_0.c86 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_rptr()
88 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_rptr()
97 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_get_rptr()
118 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_wptr()
120 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_wptr()
129 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_get_wptr()
149 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_set_wptr()
151 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_set_wptr()
160 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); in vce_v3_0_ring_set_wptr()
276 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx)); in vce_v3_0_start()
[all …]
HDmxgpu_vi.c49 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
79 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
126 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
134 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
140 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
170 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
269 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
HDgfx_v8_0.c215 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
228 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
257 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
327 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
358 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
389 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
401 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
409 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
431 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
460 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
[all …]
HDamdgpu_amdkfd_gfx_v8.c745 WREG32(mmGRBM_GFX_INDEX, gfx_index_val); in kgd_wave_control_execute()
755 WREG32(mmGRBM_GFX_INDEX, data); in kgd_wave_control_execute()
HDamdgpu_amdkfd_gfx_v9.c931 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); in kgd_wave_control_execute()
941 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); in kgd_wave_control_execute()
HDgfx_v9_0.c1690 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in gfx_v9_0_select_se_sh()
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
HDvega10_powertune.c948 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_cac_driving_se_didt_config()
963 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_cac_driving_se_didt_config()
999 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_didt_config()
1008 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_didt_config()
1060 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_se_edc_config()
1071 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_config()
1110 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_edc_config()
1119 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_edc_config()
1169 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_force_stall_config()
HDsmu7_powertune.c973 value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX); in smu7_enable_didt_config()
978 cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value); in smu7_enable_didt_config()
1005 cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value2); in smu7_enable_didt_config()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h750 #define mmGRBM_GFX_INDEX 0x200B macro
HDgfx_7_0_d.h783 #define mmGRBM_GFX_INDEX 0xc200 macro
HDgfx_7_2_d.h796 #define mmGRBM_GFX_INDEX 0xc200 macro
HDgfx_8_0_d.h871 #define mmGRBM_GFX_INDEX 0xc200 macro
HDgfx_8_1_d.h871 #define mmGRBM_GFX_INDEX 0xc200 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h4851 #define mmGRBM_GFX_INDEX … macro
HDgc_9_2_1_offset.h5094 #define mmGRBM_GFX_INDEX … macro
HDgc_9_1_offset.h5138 #define mmGRBM_GFX_INDEX … macro