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Searched refs:mmGDS_PS1_CTXSW_CNT3 (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_8_0_d.h2544 #define mmGDS_PS1_CTXSW_CNT3 0x335e macro
HDgfx_8_1_d.h2523 #define mmGDS_PS1_CTXSW_CNT3 0x335e macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h3159 #define mmGDS_PS1_CTXSW_CNT3 … macro
HDgc_9_2_1_offset.h3396 #define mmGDS_PS1_CTXSW_CNT3 … macro
HDgc_9_1_offset.h3446 #define mmGDS_PS1_CTXSW_CNT3 … macro