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Searched refs:mmGDS_GWS_VMID0 (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_7_0_d.h2249 #define mmGDS_GWS_VMID0 0x3320 macro
HDgfx_7_2_d.h2271 #define mmGDS_GWS_VMID0 0x3320 macro
HDgfx_8_0_d.h2469 #define mmGDS_GWS_VMID0 0x3320 macro
HDgfx_8_1_d.h2448 #define mmGDS_GWS_VMID0 0x3320 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h3045 #define mmGDS_GWS_VMID0 … macro
HDgc_9_2_1_offset.h3282 #define mmGDS_GWS_VMID0 … macro
HDgc_9_1_offset.h3332 #define mmGDS_GWS_VMID0 … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v9_0.c3417 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, in gfx_v9_0_ring_emit_gds_switch()
HDgfx_v8_0.c175 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},