Home
last modified time | relevance | path

Searched refs:mmGB_TILE_MODE0 (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDvi.c495 {mmGB_TILE_MODE0},
588 case mmGB_TILE_MODE0: in vi_get_register_value()
620 idx = (reg_offset - mmGB_TILE_MODE0); in vi_get_register_value()
HDcik.c970 {mmGB_TILE_MODE0},
1064 case mmGB_TILE_MODE0: in cik_get_register_value()
1096 idx = (reg_offset - mmGB_TILE_MODE0); in cik_get_register_value()
HDgfx_v8_0.c2407 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2597 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2786 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2989 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3191 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3362 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3538 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h658 #define mmGB_TILE_MODE0 0x2644 macro
HDgfx_7_0_d.h692 #define mmGB_TILE_MODE0 0x2644 macro
HDgfx_7_2_d.h705 #define mmGB_TILE_MODE0 0x2644 macro
HDgfx_8_0_d.h777 #define mmGB_TILE_MODE0 0x2644 macro
HDgfx_8_1_d.h777 #define mmGB_TILE_MODE0 0x2644 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h938 #define mmGB_TILE_MODE0 … macro
HDgc_9_2_1_offset.h878 #define mmGB_TILE_MODE0 … macro
HDgc_9_1_offset.h912 #define mmGB_TILE_MODE0 … macro