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Searched refs:mmGB_ADDR_CONFIG (Results 1 – 14 of 14) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDmxgpu_vi.c129 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
272 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
HDsoc15.c293 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
321 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) in soc15_get_register_value()
HDvi.c493 {mmGB_ADDR_CONFIG},
584 case mmGB_ADDR_CONFIG: in vi_get_register_value()
HDcik.c968 {mmGB_ADDR_CONFIG},
1060 case mmGB_ADDR_CONFIG: in cik_get_register_value()
HDgfx_v8_0.c218 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
328 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
359 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
392 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
404 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
492 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
588 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
693 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
3863 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_gpu_init()
HDgfx_v9_0.c111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
1200 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); in gfx_v9_0_gpu_early_init()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h654 #define mmGB_ADDR_CONFIG 0x263E macro
HDgfx_7_0_d.h688 #define mmGB_ADDR_CONFIG 0x263e macro
HDgfx_7_2_d.h701 #define mmGB_ADDR_CONFIG 0x263e macro
HDgfx_8_0_d.h773 #define mmGB_ADDR_CONFIG 0x263e macro
HDgfx_8_1_d.h773 #define mmGB_ADDR_CONFIG 0x263e macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h928 #define mmGB_ADDR_CONFIG … macro
HDgc_9_2_1_offset.h868 #define mmGB_ADDR_CONFIG … macro
HDgc_9_1_offset.h902 #define mmGB_ADDR_CONFIG … macro