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Searched refs:mmCP_ROQ1_THRESHOLDS (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
HDgfx_6_0_d.h530 #define mmCP_ROQ1_THRESHOLDS 0x21D5 macro
HDgfx_7_0_d.h534 #define mmCP_ROQ1_THRESHOLDS 0x21d5 macro
HDgfx_7_2_d.h547 #define mmCP_ROQ1_THRESHOLDS 0x21d5 macro
HDgfx_8_0_d.h600 #define mmCP_ROQ1_THRESHOLDS 0x21d5 macro
HDgfx_8_1_d.h600 #define mmCP_ROQ1_THRESHOLDS 0x21d5 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
HDgc_9_0_offset.h214 #define mmCP_ROQ1_THRESHOLDS … macro
HDgc_9_2_1_offset.h208 #define mmCP_ROQ1_THRESHOLDS … macro
HDgc_9_1_offset.h214 #define mmCP_ROQ1_THRESHOLDS … macro